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Freescale Semiconductor, Inc.
MC92314
Freescale Semiconductor, Inc...
DVB-T Single Chip Demodulator Application Note Authors Christoph Patzelt (Motorola), Adrian Turner (NDS)
(Single Chip DVB-T Demodulator) Rev. 1.3
Date: November 30, 1998 3:37 pm
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) MOTOROLA, INC. 1997 All Rights Reserved
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Rev. 1.3 Revision Status: Version 1.2 Finalised.
Summary of Changes or Updates: * Significant reduction in external intervention. Rev. 1.1: * Changes to VCXO LPF included.
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Rev. 1.2: * Added CSE register to OFDM block register map. * Added AGC Fix and VCXO Fix descriptions. Rev. 1.3: * Included performance values and power consumption values. * Included suggestions to speed up acquisition (AFC Sweep Start, fixing FEC coderate). * Added Timing Diagram * Added BGA package information * Added VCXO tolerance requirement
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Single Chip DVB-T Demodulator
Table of Contents
Section 1
SYSTEM OVERVIEW 1.1 General Description ............................................................................................1-1 1.2 Considerations on Terrestrial Transmission .......................................................1-2 1.2.1 Echoes on the Transmission Path.................................................................1-2 1.2.2 Noise .............................................................................................................1-3 1.3 Advantages of the OFDM Transmission Scheme...............................................1-3 1.4 Overview of the DVB-T System ..........................................................................1-4 1.4.1 Modulation Scheme.......................................................................................1-4 1.4.2 OFDM Block ..................................................................................................1-6 1.4.3 FFT Block ......................................................................................................1-6 1.4.4 Forward Error Correction Block.....................................................................1-6 1.4.4.1 Viterbi Decoder...................................................................................1-6 1.4.4.2 Convolutional Deinterleaver ...............................................................1-7 1.4.4.3 Reed-Solomon Decoder .....................................................................1-7 1.4.4.4 Energy Dispersal Removal (Descrambling)........................................1-7 1.5 References .........................................................................................................1-8
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Section 2
PINOUT & SIGNAL DESCRIPTION OF THE MC92314 2.1 Pinout for the 160PQFP Package.......................................................................2-2 2.2 Pinout for the 169BGA Package.........................................................................2-3 2.3 Pin Description of the Single Chip DVB-T Demodulator MC92314 ....................2-4
Section 3
DEVICE DESCRIPTION 3.1 Complete DVB-T Digital Frontend ......................................................................3-1 3.2 Component Descriptions ....................................................................................3-1 3.2.1 2K-FFT Processor Block ...............................................................................3-1 3.2.2 2K-OFDM Demodulator Block.......................................................................3-2 3.2.2.1 I/Q-Demodulator .................................................................................3-3
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Table of Contents
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Section 4
4.1 General Purpose Outputs ...................................................................................4-1 4.2 I2C Interface .......................................................................................................4-1 4.2.1 I2C Functionality............................................................................................4-2 4.2.1.1 Start Condition....................................................................................4-2 4.2.1.2 Stop Condition ....................................................................................4-3 4.2.1.3 Transmitting "1" and "0" ......................................................................4-3 4.2.1.4 Data Transfer Sequence ....................................................................4-3 4.2.1.5 Accessing Registers via I2C...............................................................4-4 4.2.1.6 I2C Interface of the MC92314 ............................................................4-5 4.2.2 I2C Register Maps of the MC92314 ..............................................................4-7 4.2.2.1 Register Map for the OFDM Part........................................................4-8 4.2.2.2 Register Map for the FEC Part .........................................................4-17 4.3 Tuner Interface .................................................................................................4-25 4.3.1 General Tuner Characteristics ....................................................................4-25 4.3.2 Clock Signals...............................................................................................4-26 4.3.3 Input from the Tuner Analog-to-Digital Converter .......................................4-27
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DVB-T DEMODULATOR INTERFACES
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3.2.2.2 Derotator.............................................................................................3-3 3.2.2.3 Time Synchronisation .........................................................................3-3 3.2.2.4 Channel Estimation ............................................................................3-4 3.2.2.5 Channel Estimation RAM ...................................................................3-4 3.2.2.6 Channel Correction.............................................................................3-4 3.2.2.7 Channel State Estimation ...................................................................3-4 3.2.2.8 Inner Deinterleaver .............................................................................3-5 3.2.2.9 Symbol Demapper and Bit Deinterleaver ...........................................3-5 3.2.2.10 Data Formatter ...................................................................................3-5 3.2.3 FEC Block .....................................................................................................3-6 3.2.3.1 Node Synchroniser .............................................................................3-6 3.2.3.2 Viterbi Error Correction.....................................................................3-12 3.2.3.3 Frame Synchronisation.....................................................................3-18 3.2.3.4 Deinterleaver ....................................................................................3-23 3.2.3.5 Reed-Solomon Decoder ...................................................................3-24 3.2.3.6 Descrambler .....................................................................................3-28
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Table of Contents
4.3.4 Tuner Control signals from the MC92314 ...................................................4-27 4.3.4.1 VCXO Control Loop..........................................................................4-28 4.3.4.2 AGC Control Loop ............................................................................4-28 4.4 MPEG-2 Output Interface of the MC92314.......................................................4-28 4.5 References .......................................................................................................4-29
Section 5
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USAGE AND PERFORMANCE OF MOTOROLA'S SINGLE-CHIP DVB-T DEVICE 5.1 Remarks on the Circuit Diagram.........................................................................5-1 5.2 Initialising the Chipset.........................................................................................5-1 5.2.1 Setup of the OFDM Block..............................................................................5-2 5.2.1.1 Registers of the OFDM Block .............................................................5-2 5.3 Monitoring the DVB-T Single Chip......................................................................5-2 5.3.1 Status Information of the OFDM Block..........................................................5-2 5.3.1.1 Hardware pins ....................................................................................5-2 5.3.1.2 Lock Status Registers.........................................................................5-2 5.3.1.3 Usage of the AGC Feedback Register ...............................................5-3 5.3.2 Status Information of the FEC Block .............................................................5-3 5.3.2.1 Hardware Pins ....................................................................................5-3 5.3.2.2 Software Registers .............................................................................5-3 5.3.2.3 FEC Block QVAL Values corresponding to BER values ....................5-3 5.4 Performance Considerations ..............................................................................5-4 5.4.1 Possible Changes in the OFDM Block ..........................................................5-4 5.4.1.1 Speeding up the Acquisition Time ......................................................5-4 5.4.1.2 Co-Channel Protection vs. Noise .......................................................5-6 5.4.2 Possible Changes in the FEC Block..............................................................5-6 5.4.2.1 Fixing the Coderate for the Viterbi Decoder .......................................5-6 5.4.2.2 Adjusting the MPEG Frame Synchroniser..........................................5-6 5.5 MC92314 Performance.......................................................................................5-7 5.5.1 Performance in a typical Consumer Application............................................5-7 5.5.1.1 Typical Lock Performance ..................................................................5-7 5.5.1.2 Noise and Interference Performance..................................................5-9 5.6 References .......................................................................................................5-10
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Table of Contents
Section 6
ELECTRICAL CHARACTERISTICS 6.1 MC92314 Electrical Considerations....................................................................6-1 6.2 MC92314 DC Electrical Specifications ...............................................................6-3 6.3 MC92314 Timing Characteristics........................................................................6-4
Section 7
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MECHANICAL CHARACTERISTICS
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7.1 Outlines of the 160PQFP Package.....................................................................7-1 7.2 Outlines of the 169BGA Package .......................................................................7-3
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System Overview
SECTION 1 SYSTEM OVERVIEW
In this Application Note Motorola's single chip demodulator and FEC for DVB-T receivers along with the usual application is described. This section covers the overall descriptions as well as an introduction into the DVB-T standard, supporting the understanding of the special features of the OFDM system.
1.1 General Description
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* Supported DVB-T modulation schemes: QPSK, 16-QAM and 64-QAM. * Automatic lock onto all specified guard interval lengths (1/32, 1/16, 1/8, 1/4). * Data input: 8 Bit TTL compatible 2's complement or offset binary. * Channel estimation and correction using the pilot carriers. * I2C compatible interface (M-Bus). * Transmission Parameter Signalling (TPS) data is decoded and made available to the system controller via M-Bus. * Processing of one block of 2048 complex samples (i.e. one 2K-OFDM symbol) in 224 ms. * FFT input wordlength 8 bit, output accuracy 12 bit. * Overflow on certain OFDM subcarriers due to co-channel interferes is prevented internally.
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* C/N performance according to Reference [1-1] Annex A with a degradation margin of 3 dB.
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* Usable for 8 MHz, 7 MHz and 6 MHz channel bandwidth by adjusting the clock rate.
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Important capabilities of the FFT/OFDM block:
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There are two main sections in the chip, providing the functions necessary to obtain a complete MPEG-2 transport stream out of one real IF-sampled DVB-T signal. The steps necessary are OFDM demodulation and FEC decoding, corresponding to the three separate devices described in Reference [1-4]:
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* 169 BGA package
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* 160 pin QFP package
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* 0.35mm CMOS process at 3.3 V.
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Before describing the important specialities of the DVB-T system itself the key features of Motorola's single chip are outlined.
MOTOROLA 1-1
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System Overview
Key items of the FEC part include: * Maximum 37 Mbit/s output rate. * 3 Bit soft-decision input matched to the output of the OFDM block. * Code rate 1/2 and depunctured rates of 2/3, 3/4, 5/6, and 7/8. * Automatic or manual rate selection. * Viterbi decoder survivor depth 96 * Signal quality output data. * DVB compliant 12 x 17 Forney Convolutional Deinterleaver * Reed-Solomon (204, 188, 8) decoder as specified by DVB * DVB Descrambler for Energy Dispersal & inverted Sync Byte removal * setting of "transport_error_indicator" bit in the MPEG2 output stream (MSB of first byte immediately following the Sync Byte) * Bit Error Rate (BER) and uncorrectable Frame Error (BAD) monitoring
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1.2 Considerations on Terrestrial Transmission
One of the most important aspects in designing a transmission system is to chose the modulation scheme that fits best to the characteristics of the transmission channel employed. Comparing the terrestrial channel in the UHF band with the channels of the satellite or cable system yields several important differences that exclude the modulation schemes used there from an efficient usage in the terrestrial channel.
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In Figure 1-1 a typical environment for terrestrial reception is given. The antenna of the stationary receiver receives the signal belonging to the direct path from the transmitter as well as delayed echoes e.g. from buildings (this is called a Ricean channel). In contrast to this a portable receiver may receive only echoes without a signal direct from the transmitter (Rayleigh channel characteristics).
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1.2.1 Echoes on the Transmission Path
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System Overview
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Figure 1-1. Possible echo constellation In the well known analog TV transmission systems such echoes appear as ghost pictures on the screen, but as long as they don't get too strong the original information remains visible, at the penalty of reduced picture quality.
1.2.2 Noise
Another impairment on every transmission channel is the addition of noise. Due to many reasons (e.g. thermal noise, impulse noise from ignition sources) the signal quality degrades with increasing distance from the transmitter. On the analog TV picture the different noise sources decrease the quality of the picture, but as long as the synchronisation circuitry remains in lock even heavily distorted pictures deliver visible information to the viewers.
1.3 Advantages of the OFDM Transmission Scheme
In contrast to this the behaviour of analog systems outlined in the paragraphs above the behaviour of digital transmission systems is different. The picture contents are mapped into digital signals, transmission impairments lead to transmission errors, resulting in bit errors of the received datastream. Due to the high compression ration of the source encoded MPEG-2 transport stream used in the DVB systems even single bit errors may have a severe impact on the picture quality. Without careful system layout, taking into account the characteristics of the transmission channel, the performance of a digital transmission system may be very poor. The problems mentioned above can be circumvented successfully leading to the present system for digital terrestrial transmission. One of the main points is the Orthogonal Frequency Division Multiplex (OFDM) scheme. The following list gives a short overview about the key features of the DVB-T standard:
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA 1-3
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System Overview
* Divide the whole available bandwidth into a large number of subchannels with different frequencies (Frequency Division Multiplex). * each subchannel is independent form all others (Orthogonality). * To combat the echoes in the terrestrial channel a guard interval is used to absorb them. * A certain amount of redundancy is added to the bits at the transmitter side, allowing powerful error correction techniques in the receiver. In principle the whole available bandwidth is divided into a large number N (e.g. 2048) of separate narrowband subchannels (the OFDM subcarriers). Data transmission on each subcarrier frequency is independent from and in parallel with the other subcarriers, leading to a very low datarate on each subcarrier compared to the overall transmission capacity. The splitting into the subchannels including the modulation onto the subcarriers can be done very efficiently by performing an Inverse Fast Fourier Transform (FFT) to the data to be transmitted. In turn the receiver must do a FFT to obtain the original information. Following the usual terms of digital signal processing the region before the IFFT in the transmitter and after the FFT in the receiver is called `frequency domain' and in contrast to it the signal after the IFFT (in the transmitter) until before the FFT (in the receiver) is associated with the `time domain'. All these steps together allow the realisation of a robust transmission scheme specially adapted to the terrestrial channel. Advances in silicon technology enable the implementation of the advanced signal processing algorithms necessary at costs suitable to the consumer electronics industry. Additional information on the OFDM system can be obtained from Reference [1-2] and Reference [1-3].
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1.4 Overview of the DVB-T System
After thorough investigation of the requirements the standard for digital terrestrial television was finalised in 1996 (see Reference [1-1]). In line with the standards for the satellite system (DVBS) and the cable system (DVB-C) it specifies all the transmission parameters for the broadcasting of services via terrestrial (e.g. UHF) channels.
1.4.1 Modulation Scheme
The standard covers the Orthogonal Frequency Division Multiplex (OFDM) scheme, using OFDM symbol lengths of either 2048 (2K) or 8192 (8K) complex-valued samples. The integrated circuit covered in this document can deal only with the 2K-system, so the 8K system is not covered here. Figure 1-2 gives a block diagram of the complete DVB-T transmission system, the blocks marked with thick lines are unique to the terrestrial system, whereas the other blocks are identical to the satellite standard DVB-S. In this diagram also the basic parameters of the transmission parameters are given, for a more detailed description see Reference [1-1]
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MPEG-2 TS
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Sync-Inversion Scrambling P(x)=1+x14+x15
FEC-Encod. and Interl.
Inner Interleaving
Mapper and Modulator QPSK, 16-QAM or 64-QAM,
Frame-Adapt. OFDM-Mod. Guard-Int. Pilot insertion 2 K IFFT Different guard interval lengths possible
Figure 1-2. DVB-T transmission system
Upconversion Amplification UHF Range 470-862 MHz
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RS (204,188) of GF (256) Bit-Interleaving with Block size Interleaving depth I=12; 72 Bits Cell memory M=17 byte Symbol Convolutional Encoding (Frequency)(G1=171, G2=133), Interleaving Mothercoderate 1/2, Possible Coderates 2/ , 3/ , 5/ , 7/ 3468
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Non-uniform Modulation possible
Terrestrial Channel
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Synchron. OFDM Demodulation
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Downconversion I,QDemodulation
Sync-Inversion Descrambling
FEC-Decod. Deinterleaving
Inner Deinterleaving
Demapping
System Overview
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System Overview
1.4.2 OFDM Block
The OFMD block performs the functions given in the blocks `Synchronisation', `Demapping' and `Inner Deinterleaving' in Figure 1-2. This includes all the necessary synchronisation tasks, OFDM-related deinterleaving, demapping of the constellation diagram, generation of softdecision information and output formatting. This block is designed to work directly with the FFT block. Important capabilities are: * Usable for 8 MHz, 7 MHz and 6 MHz channel bandwidth by adjusting the clock rate. * C/N performance according to Reference [1-1] Annex A with a degradation margin of 3 dB.
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* Supported DVB-T modulation schemes: QPSK, 16-QAM and 64-QAM.
1.4.3 FFT Block
Main features of the FFT block are:
* FFT input wordlength 8 bit, output accuracy selectable between 10 and 12 bit. * Overflow on certain OFDM subcarriers due to co-channel interferes is handled internally.
1.4.4 Forward Error Correction Block
The FEC part of the DVB-T transmission is located in the blocks `FEC-Decoding', `Deinterleaving', `Sync-Inversion' and Descrambling. All these tasks are handled by the FEC block. The FEC scheme itself consist of the inner Viterbi decoder and the outer RS decoder. 1.4.4.1 Viterbi Decoder The Viterbi decoder block is DVB compliant with all the coderates available according to the specification. Its main features are: * Maximum 37 Mbit/s output rate. * Constraint length 7, generator polynomial (1718, 1338)
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* Processing of one block of 2048 complex samples (i.e. one 2K-OFDM symbol) in 224 s.
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The FFT block performs the OFDM demodulation in the true sense of the word. It gets the time domain information from the OFDM block, performs a Fast Fourier Transform on it and delivers the frequency domain information, i.e. the constellation diagram (suffering from the channel impairments) back again to the OFDM block.
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* Transmission Parameter Signalling (TPS) data is decoded and made available to the system controller via M-Bus.
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* I2C compatible interface (M-Bus) to the system controller.
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* Channel estimation and correction using the pilot carriers.
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* Data input: 8 Bit TTL compatible 2's complement or offset binary.
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* Automatic lock on all specified guard interval lengths (1/32, 1/16, 1/8, 1/4).
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System Overview
* 3 Bit soft-decision input in suited to the output of the OFDM block. * Code rate 1/2 and depunctured rates of 2/3, 3/4, 5/6, and 7/8. * Automatic or manual rate selection. * Programmable internal synchronizer. * Provision for external synchronization. * Survivor depth 96 * No internal APLL needed, clock is provided by the OFDM block. * Signal quality output data. 1.4.4.2 Convolutional Deinterleaver To achieve the optimal performance of any concatenated coding scheme there must be an interleaver in the transmitter between the inner and outer encoder. This interleaver distributes the bytes in a pseudo random order before feeding them into the inner encoder. In turn the deinterleaver in the receiver rearranges the original order, spreading error bursts provoked by overloading the inner decoder due to bad channel conditions. In case of the DVB system the interleaving scheme uses a Convolutional 12x17 Forney Interleaver: Every 204 bytes of data are interleaved (reordered) at the transmitter and deinterleaved in the receiver using a Convolutional Deinterleaver with I=12 branches and M=17 byte storage cells as defined by the DVB Specifications. 1.4.4.3 Reed-Solomon Decoder The FEC block contains a complete Reed-Solomon decoder as specified by DVB for digital receiver applications (204, 188) of GF(256), that means input blocks with 188 byte in length, added redundancy of 16 checkbytes leading to 204 bytes output block length. The block will accept data from the Viterbi decoder and deliver an MPEG-2 transport stream to the Set-Top Box core demultiplexer. 1.4.4.4 Energy Dispersal Removal (Descrambling) The MPEG-2 data (excluding Sync Bytes) are randomised for Energy Dispersal in the transmitter. This block reverses the process and re-inverts the inverted Sync Byte prior to delivering the data to the MPEG-2 Transport Demultiplexer. It is the last step in the frontend processing chain. The main features of the deinterleaver, RS decoder and descrambling block are given below: * 37 MBit/s typical input and output data rates * optimized Frame Synchronizer performance for DVB parameters * DVB compliant 12x17 Forney Deinterleaver * Reed-Solomon (204,188,8) decoder as specified by DVB * DVB Descrambler for Energy Dispersal & inverted Sync Byte removal
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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System Overview
* setting of "transport_error_indicator" bit in the MPEG2 output stream (MSB of first byte immediately following the Sync Byte) * Bit Error Rate (BER) and uncorrectable Frame Error (BAD) monitoring * 180o input data stream phase error correction
1.5 References
[1-1] ETSI (European Telecommunication Standards Institute): Digital broadcasting systems for television, sound and data services; Framing structure, channel coding and modulation for digital terrestrial television. Draft prETS 300 744, September 1996.
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[1-2] M. Alard, R. Lassalle: Principles of modulation and channel coding for digital broadcasting for mobile receivers. EBU Collected Papers on concepts for sound broadcasting into the 21st century, August 19988, pp. 47-69. [1-3] J. Gledhill, S. Anikhindi, P. Avon: The transmission of digital television in the UHF band using Orthogonal Frequency Division Multiplex. Proceedings of the 6th International IEE Conference on Digital Processing of Signals in Communications, IEEE Conf. Publ. No. 340, pp. 175-180, September 1991.
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[1-4] C. Patzelt, M. Drozd, S. Anikhindi: MC92307 MC92308 MC92309 DVB-T, Chipset Application Note Version 1.1; Motorola; July 1998.
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Pinout & Signal Description of the MC92314
SECTION 2 PINOUT & SIGNAL DESCRIPTION OF THE MC92314
Motorola's DVB-T demodulator is available in a 160QFP package as well as in a 169BGA. The pinout of this packages as well as the input and output lines are given in Figure 2-1, Figure 2-2 and Table 2-1. The mechanical dimensions of the package are given in Section 7. The supply voltage of the IC is 3.3 V, its power consumption is app. 1.7 W in a typical DVB-T application as it is described Section 5.
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 2-1
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Pinout & Signal Description of the MC92314
2.1 Pinout for the 160PQFP Package
ADCDATA2 VSS reserved (VSS) VDD reserved (VSS) ADCDATA1 VSS reserved (VSS) VDD reserved (VSS) ADCDATA0 VSS VDD ADCDATA-1 VSS ADCDATA-2 VDD INSYNC VLOCK TPSLOCKB reserved (open) AFCLOCK CLKLOCK VSS reserved (open) RESB VDD reserved (open) VSS reserved (open) TRERROR VDD reserved (open) VSS reserved (open) TRSTART reserved (open) VDD reserved (open) TRVALID
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ADCDATA3 reserved (VSS) VSS reserved (VSS) VDD ADCDATA4 reserved (VSS) VSS reserved (VSS) VDD ADCDATA5 reserved (VSS) VSS reserved (VSS) VDD ADCDATA6 reserved (VSS) VSS reserved (VSS) VDD ADCDATA7 reserved (VSS) VSS reserved (VSS) VDD reserved (VSS) reserved (VSS) VSS reserved (VSS) VDD reserved (VSS) VSS CLKEN18 reserved (VSS) VDD AGCCTLP reserved (VSS) VSS reserved (VSS) AGCCTLN
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TRCLK reserved (open) VSS reserved (open) VDD TRDOUT7 reserved (open) VSS reserved (open) VDD TRDOUT6 reserved (open) VSS reserved (open) VDD TRDOUT5 GP3 VSS GP2 VDD TRDOUT4 GP1 VSS GP0 VDD TRDOUT3 reserved (open) VSS reserved (open) VDD TRDOUT2 reserved (open) VSS reserved (open) VDD TRDOUT1 reserved (open) VSS reserved (open) TRDOUT0
MOTOROLA 2-2
CLKCTLP reserved (VSS) VDD reserved (VSS) VSS CLKCTLN reserved (VSS) VDD reserved (VSS) VSS SCL reserved (VSS) VDD reserved (VSS) VSS SDA reserved (VSS) VDD reserved (VSS) VSS CLK reserved (VSS) VDD reserved (VSS) VSS MBUSID0 reserved (VSS) VDD reserved (VSS) VSS MBUSID1 reserved (VSS) VDD reserved (open) VSS MBUSID2 reserved (open) VDD reserved (open) MBUSID3
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Figure 2-1. Pinout for the 160PQFP
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For More Information On This Product, Go to: www.freescale.com
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Pinout & Signal Description of the MC92314
2.2 Pinout for the 169BGA Package
View from top, x-ray through package.
1 A B C D E F G H J K L M N 2 3 4 5 6 7 8
(VSS)
9
10
11
12
13
ADCDATA3ADCDATA4 (VSS)
ADCDATA5ADCDATA6ADCDATA7 (VSS)
CLKEN18 AGCCTLP (VSS)
AGCCTLN CLKCTLP
ADCDATA2 (VSS)
(VSS)
(VSS)
(VSS)
(VSS)
(VSS)
OPEN8
(VSS)
(VSS)
(VSS)
(VSS)
(VSS)
Freescale Semiconductor, Inc...
TRERROR (OPEN)
Pr
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CLKLOCK
RESB
x
im
AFCLOCK (OPEN)
VDD
in
VDD
ar
VLOCK
TPSLOCK (OPEN) B
VDD GND
GND
y
In
(VSS)
INSYNC
VDD
VDD
GND
GND
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ADCDATA0 (VSS)
x
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ADCDATA1 (VSS)
(VSS)
GND
VDD
VDD
VDD
VDD
io n
(VSS)
(VSS)
x
(VSS)
x
VDD
(VSS)
VDD
x
OPEN9
VDD
(VSS)
(VSS)
VDD
GND
CLKCTLN
MSCL
(VSS)
VDD
GND
GND
GND
GND
GND
VDD
x
(VSS)
MSDA
GND
GND
GND
VDD
VDD
(VSS)
CLK
GND
GND
GND
GND
GND
(VSS)
(VSS)
(VSS)
GND
GND
GND
GND
GND
VDD
VDD
MBUSID0 (VSS)
VDD GND
GND
GND
GND
GND
GND
VDD
(VSS)
MBUSID1 (VSS)
(OPEN)
GND
VDD
VDD
VDD
VDD
VDD
GND
(OPEN)
MBUSID2
(OPEN)
(OPEN)
(OPEN)
VDD
(OPEN)
x
VDD
GP2
VDD
x
(OPEN)
x
(OPEN)
MBUSID3
TRSTART (OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
GP3
GP1
(OPEN)
(OPEN)
(OPEN)
(OPEN)
TRDOUT0
(OPEN)
TRVALID
TRCLK
TRDOUT7 (OPEN)
TRDOUT6 TRDOUT5 TRDOUT4
GP0
TRDOUT3 TRDOUT2 TRDOUT1 (OPEN)
Figure 2-2. Pinout for the 169BGA
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
MOTOROLA 2-3
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Freescale Semiconductor, Inc.
Pinout & Signal Description of the MC92314
2.3 Pin Description of the Single Chip DVB-T Demodulator MC92314
The description of the MC92314 pinout is given in the table below: Table 2-1. MC92314 Pin List
SIGNAL CLK RESB CLKEN18 ADCDATA[7:0] PIN-NR. 61 135 33 21, 16, 11, 6, 1, 160, 155, 150 147, 145 41 46 36 40 56 51 80, 76, 71, 66 104, 102, 99, 97 130 121 125 120 FUNCTIONALITY Common clock input (36.57 MHz) Reset (asynchronous) ADC data strobe ADC input TYPE TTL - IN TTL - IN TTL - IN TTL - IN reserved (VSS) TTL - OUT TTL - OUT TTL - OUT TTL - OUT TTL - OD TTL - IN TTL - IN TTL - OUT TTL - OUT TTL - OUT TTL - OUT TTL - OUT ACTIVE high low high high
Freescale Semiconductor, Inc...
ADCDATA[-1:-2] CLKCTLP CLKCTLN AGCCTLP AGCCTLN MSDA MSCL MBUSID[3:0]] GP[3:0] TRERROR TRVALID TRSTART TRCLK
10-Bit extension for future 8K device ADC clock control (+) ADC clock control (-) Analogue AGC control (+) Analogue AGC control (-)
N/A high low high low N/A high high high high high high high
I2C compatible control bus, data pin I2C compatible control bus, variable ID selector General Purpose Output pins
in
TRDOUT[7:0]
INSYNC VLOCK TPSLOCKB AFCLCK CLKLCK
Pr
115, 110, 105, 100, 95, 90, 85, 81 143 141 139 138 142
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MPEG-2 Frame Error Indicator MPEG-2 Byte Valid Indicator MPEG-2 Byte Clock
MPEG-2 Sync Byte Indicator
MPEG-2 Transport Stream Byte Output
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In
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I
2C
compatible control bus, clock pin
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TTL - OUT
high
FEC Frame Synchronization Status Viterbi Decoder Synchronization Status TPS Data Valid indicator (inverted) AFC status indicator Time Synchronization state indicator
TTL - OUT TTL - OUT TTL - OUT TTL - OUT TTL - OUT
high high low high high
NOTE The pins marked with (VSS) in the BGA pinout must be tied to VSS. As they are reserved pins they need not to be connected directly to VSS, instead of a pulldown resistor of about 10 K is sufficient. Similar the pins `(OPEN)' must be left unconnected.
MOTOROLA 2-4
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
SECTION 3 DEVICE DESCRIPTION
In this section the chipset as a whole as well as the operation of the several components are described.
3.1 Complete DVB-T Digital Frontend
Motorola's terrestrial chipset builds a complete digital frontend for the DVB-T system, it performs according to the following functional diagram:
Freescale Semiconductor, Inc...
io n
2
MBUS TRERROR TRVALID TRTART TRCLK TRDOUT
IC
2
m
RF-Input
Tuner Core
A D
8
RESB ADCDATA
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CLKEN18
at
MC92314 2K DVB-T
AGC AGC CTLP CTLN
1/2
CLK
In
CLK CLK CTLP CTLN
8
MPEG-2 Transport Stream
Tuner
Whereas Motorola's chipset covers all the digital functions required by the standard, the analog parts (RF amplification, RF filtering, downconversion, AGC, clock generation and ADconversion) are located in the DVB-T tuner. The RF signal obtained by the antenna has to be fed into the tuner core, given that the C/N of the signal is high enough for the demodulation the receiver frontend will lock onto it and produce the transmitted transport stream ready to deliver it to the MPEG-2 demultiplexer.
3.2 Component Descriptions
After giving the overall functions of the complete digital frontend in the last paragraph we go into more detail of the individual components:
3.2.1 2K-FFT Processor Block
Integrated into the MC92314 is a pipelined Fast Fourier Transformation (FFT) processor with a blocklength of 2048 complex samples. It is especially designed for use in digital terrestrial Set-
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Figure 3-1. Block Diagram of a complete DVB-T Frontend
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VCXO
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MOTOROLA 3-1
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Freescale Semiconductor, Inc.
Device Description
Top boxes according to the DVB-T standard for 2K transmission. One block of 2048 complex samples can be processed in 224 s
NOMUX DIN 8 12 DOUT
DINR
8
Input Buffer
16
FFT (11 stages) incl. Rounding
24
FFTSTART
Output Reorder Buffer
12
DOUTR
RESB
Freescale Semiconductor, Inc...
CLK
Twiddle Factor ROM Control
FFTSTART
RES[1:0] REVRSB
MOTOROLA 3-2
Pr
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The MC92314 contains also a Demodulator for the Orthogonal Frequency Division Multiplex transmission scheme according to the 2K-mode of the ETSI specification for digital terrestrial transmission (see reference [1-1]). Together with the 2K FFT block described in the previous paragraph it includes all the functions required to demodulate the information transmitted in one single UHF channel. In Figure 3-3 the block diagram of the OFDM block is given, followed by the description of the functional blocks.
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3.2.2 2K-OFDM Demodulator Block
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Figure 3-2. Block Diagram of the FFT Processor
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For More Information On This Product, Go to: www.freescale.com
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OFFSET
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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SYMSYNC
Freescale Semiconductor, Inc.
Device Description
CLK Loop Filter & DAC Clock VCXO
Time Sync (Coarse & Fine)
FFT Block
Data Formatter
Control G1, G2 Data
From ADC Received Data
I/Q Demodulator & Derotator Channel Data RAM
Extracted Pilots
Symbol Deinterleaving & Demapping
AFC
Freescale Semiconductor, Inc...
AGC AGC-DAC AGC
3.2.2.2 Derotator Carrier frequency offsets resulting from local oscillator offsets in the tuner are removed digitally by means of a NCO and a phase accumulator, that are controlled by the Automatic Frequency Control (AFC). During the acquisition phase (when locking onto a DVB-T transmission) the AFC circuit sweeps permanently through the available range until the correct frequency offset has been detected. During the tracking phase the control signal for the phase increment is derived from the pilot carriers in the frequency domain. 3.2.2.3 Time Synchronisation The Time Synchronisation (separated in the coarse synchronisation valid during the acquisition phase and the fine synchronisation for tracking purposes) sets the FFT window position for the real OFDM demodulation and controls the clocking of the whole chip. In the tracking mode the time synchronisation generates the VCXO control signal using the filter structure given in Figure 3-4 below. The contribution of the proportional branch and of the integrator branch can be adjusted separately using the Clock Loop Filter Coefficients (see also paragraph 4.2.2.1.5). The gain of the proportional part is set using Bits [7:4] and the gain of the integrator part is adjusted with Bits [3:0].
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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3.2.2.1 I/Q-Demodulator In this first stage the complex samples are reconstructed from the (real valued) input stream by means of a discrete Hilbert transformer. The input stream is fed into the Hilbert transformer and delayed appropriately to calculate the real and imaginary parts of the signal.
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Figure 3-3. OFDM Demodulator Part of the MC92314
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I2C & Parallel Interface
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Channel Estimation & Correction
TPS & Frame Synchronisation
Channel State Estimation
MOTOROLA 3-3
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Freescale Semiconductor, Inc.
Device Description
C_Proportional
VCXO
Phase Detector
Integrator
sd-DAC
Freescale Semiconductor, Inc...
C_Integrator
LPF
Figure 3-4. Time Synchronisation of the OFDM Block 3.2.2.4 Channel Estimation To compensate for the impairments of the terrestrial channel it is essential to estimate the channel transfer function. This estimation is done using the scattered and continual pilot carriers. As the scattered pilots change in subsequent OFDM symbols a time interpolation over 4 OFDM symbols is necessary to build a complete set of pilot information. This set contains one valid pilot sample at every 3rd carrier position. To obtain a channel estimation value so the set ends up with an estimation value for each carrier position, frequency interpolation must be performed. 3.2.2.5 Channel Estimation RAM The channel estimation RAM must store the data carriers until the channel estimation is available for a given OFDM symbol. 3.2.2.6 Channel Correction In the channel correction block the estimate of the channel transfer function is used to compensate the influence of the terrestrial transmission. In principle each data carrier's value is multiplied with the inverse of the estimate to approximate the desired flat overall frequency response to as close as possible. 3.2.2.7 Channel State Estimation To improve the efficiency of the decoding of the inner convolutional code, information about the reliability of each bit received via the transmission channel, is generated during the demodulation process. So data that were transmitted in subchannels disturbed heavily due to echoes or interference (resulting in a low SNR in these specific subchannels) are marked less reliable than those transmitted in nearly undisturbed subchannels. In the channel state estimation this
MOTOROLA 3-4 Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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For More Information On This Product, Go to: www.freescale.com
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Freescale Semiconductor, Inc.
Device Description
reliability information is generated for each carrier individually and passed together with the subcarriers data to the following stage. 3.2.2.8 Inner Deinterleaver Due to the echoes on the transmission path it is obvious that adjacent subcarriers are disturbed in a similar way: the used bandwidth of 7.61 MHz corresponds to 1705 active carriers, so the difference in the channel transfer function from one carrier to the adjacent carrier is limited. In case of a simple parallel to serial conversion adjacent bits of data would suffer from similar distortions. In this case the Viterbi decoder cannot work with its optimal performance. Instead the best performance is given if the disturbance applied to adjacent data bits is uncorrelated. To achieve this the data of all the relevant subcarriers are interleaved in the transmitter according to par. 4.3.4 in reference [1-1]. This interleaving has to be reversed prior to the demodulation. 3.2.2.9 Symbol Demapper and Bit Deinterleaver The modulated (complex valued) frequency domain samples are demapped into 2, 4 or 6 streams depending on the modulation scheme chosen. Each demodulated data bit is extended to a 3-bit soft decision value using the reliability information from the Channel State Estimation to support the following FEC. In par. 4.3.4 in reference [1-1], bit interleaving is also specified in order to disperse bursts of bit errors in the receiver after demapping the complex data symbols. This bit interleaving is reversed in the Bit Deinterleaver module. 3.2.2.10 Data Formatter This is the final stage in the OFDM specific part of the DVB-T frontend. It generates from the up to 6 bitstreams according to par. 4.3.4 in reference [1-1] the correct datastreams corresponding to the G1 and G2 data to be fed into the Viterbi decoder. Although the FEC scheme and the format of the data delivered by the OFDM block is identical to the satellite system there is a fundamental difference in clocking. In the DVB-S system the data are delivered continuously to the Viterbi decoder, where as, this cannot be the case in DVB-T. The internal clocking is uncorrelated to the transmitted data rate. Instead of going the costly way of synthesizing an extra clock signal for the Viterbi decoder, the demodulated data are output in burst mode at an average frequency corresponding to the transmitted data rate. For details see the paragraph 4.6 OFDM -> FEC Interface in reference [1-1].
Freescale Semiconductor, Inc...
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 3-5
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Freescale Semiconductor, Inc.
Device Description
3.2.3 FEC Block
The FEC block completes Motorola's DVB-T single chip demodulator by providing all the FEC functions necessary for the reception of DVB-T transmissions. It is fully compliant to the ETSI specification for digital terrestrial broadcasting (see reference [1-1]).
VLCK
VFF VEF
SR2..0
G1DATA2..0 G2DATA2..0 VDCLK DIVALID
Node Synchroniser
FIFO
Depuncturing
Viterbi Core
VO
Freescale Semiconductor, Inc...
SYMCLK
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BITCLKOUT
RERRU Error Location and Value Gener-
Check Byte Generation
SERIALIN RSONLY
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Deinterleaver Memory and Address Sequencer
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Codeword Delay FIFO
RESB
Error Detection and Evalu-
Descrambler for Energy Dispersal Removal Frame Detection
SPO7..0 DOVALID SVALO
I2C Interface
ar
SCL
SDA
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In
Frame Synchroniser
INSYNC
FSTART
3.2.3.1.1 Syndrome Based Node Synchronisation Prior to producing valid data the Viterbi decoder block must synchronise to the input data stream, including removing any phase ambiguity in the received symbols and determine the punctured code rate transmitted. The Viterbi block employs a method known as Syndrome Based Node Synchronisation to achieve both I & Q symbol and punctured rate Synchronisation. This method has certain advantages over other more common Synchronisation methods such as observation of path metric growth rates and re-encoding of the received data stream: * Path metric growth observations are relatively sensitive to input magnitude variations and require multiple estimation cycles to detect Synchronisation. * Re-encoding of the data stream (using a convolutional encoder) requires multiple estimation cycles and can increase the latency of the decoder.
MOTOROLA 3-6
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3.2.3.1 Node Synchroniser
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Figure 3-5. Block Diagram of the FEC Block
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
Syndrome based node synchronisation is independent of the average input magnitude and can also easily detect changes of the synchronisation state. The theory is based on the observation that the product of the incoming data and a syndrome (predetermined by simulation for each data rate) is zero if synchronised correctly. In any other case, the probability of 0's vs. 1's in the product increases. In the extreme case, i.e. the node synchronisation is completely wrong, the product is random and there is equiprobability of 0's and 1's. This behaviour is exploited for syndrome based node synchronisation. 3.2.3.1.2 Synchronisation States The possible states that the synchroniser has to deal with are a combination of the following factors:
Freescale Semiconductor, Inc...
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3.2.3.1.3 Synchroniser Parameters The synchroniser is based on an estimator which determines whether the received symbol sequence is in the correct synchronisation state. This estimate is based on single sided sequential probability ratio tests (SPRTs). The tests are based on the accumulation of the loglikelihood ratio (LLR) that a certain hypothesis (in-sync or out-of-sync) for the input sequence holds. A vote for a hypothesis is obtained if the accumulated LLR reaches a certain threshold. The accumulator value L is computed as shown in the flowchart in Figure .
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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If a vote for out-of-sync occurs, the synchronisation state (which is output at I2C register SYNCH_STATE) is increased to test the next hypothesis.
In
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NOTE
* Determination of the framing of the I and Q bit streams so as to extract the correct symbol. There are four possible ways to frame the two bit streams and the synchroniser must determine the correct one.
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* The phasing of the received symbols. The synchroniser must decide which of two possible states the I and Q input streams are in. They can either be processed as-is or can be rotated 90o to account for constellation rotation in the receiver.
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MOTOROLA 3-7
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Freescale Semiconductor, Inc.
Device Description
Read Syndrome Bit
Y Bit == 1
N Move To Next State
L = L + INC
L = L - DEC
Freescale Semiconductor, Inc...
L<0 N
n at
Y
Y
L=0
If the syndrome sequence is identifying an out-of-sync state (i.e. p0 = 0.5) the accumulator should be driven with approximately equal average increments towards the threshold. Obviously, the synchroniser will erroneously vote for out-of-sync condition if the channel SNR falls below a certain limit since p0 will approach 0.5 for very low SNR. * The decoder uses a fixed Increment of INC = 32. * DEC is set via I2C register DEC[4:0] and can have a maximum value of 32, default selection of DEC values according to the rate being decoded is enabled by setting the DDEC bit in the CONFIG register to 0. The default values of DEC for each of the supported rates is shown in Table 3-1. * THRES is set via I2C register THRESHOLD and can have a maximum value of 32, default selection of THRES = 8 is enabled by setting the DTHRES bit in the CONFIG register to be 0. The actual value of THRES is interpreted as x 29.
MOTOROLA 3-8
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3.2.3.1.4 Choice of DEC and THRES The constants INC, DEC and THRES influence the acquisition behaviour of the synchroniser as well as it's robustness. The constants INC and DEC should be chosen such that the accumulator is driven towards zero in the case that the syndrome sequence is identifying the in-sync state (i.e. rate of zeroes is p0).
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Figure 3-6. Synchronisation Flow
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IN-SYNCH
N
L>=THRESH
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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L=0
OUT-OF-SYNCH
Freescale Semiconductor, Inc.
Device Description
The defaults have been chosen such that the synchroniser will operate correctly (but with a performance degradation) roughly 2 dB below the output error rate, which is required for quasi error free operation (BER of the decoded stream approximately =2 x 10-4). Table 3-1. Default Settings For DEC Parameter
Lower SNR Boundary (dB)
1.2 2.0 2.4 2.9 3.5
Rate
Dec
Quasi Error Free SNR (dB)
3.0 3.5 4.0 4.5 5.2
Design Point SNR (dB)
2.15 2.49 3.00 3.51 4.10
Design Point Channel BER
0.100 0.062 0.042 0.026 0.017
1/2 2/3 3/4
29 26 25 24 23
Freescale Semiconductor, Inc...
5/6 7/8
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This is the mean time required to detect that the currently investigated synchronisation state is not the correct synchronisation state. The SARL is calculated as:
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* Reacquisition Average Run Length (RARL): This is the mean time between a erroneous detection of a change of the synchronisation state and successful acquisition of the new synchronisation state (reacquisition). The RARL is calculated as:
SARL RARL = ---------------------------------------( syncstates - 1 )
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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SARL performance is not affected by the channel SNR since the syndrome sequence is composed of equiprobable 1's and 0's for an out of synch condition and low channel SNR would also result in equiprobable 1's and 0's.
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* Short Average Run Length (SARL):
2XTHRES SARL = ---------------------------INC - DEC
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NOTES
3.2.3.1.5 Synchroniser Performance The performance of the synchroniser can be characterized by three figures:
m
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MOTOROLA 3-9
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Freescale Semiconductor, Inc.
Device Description
Where "syncstates" is given by: Table 3-2. Number of Syncstates in Code Rates
Rate
1/2 2/3 3/4 5/6 7/8
Synchstates
2 6 4 6 8
NOTE
Freescale Semiconductor, Inc...
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* Long Average Run Length (LARL): This is the mean time until the algorithm incorrectly indicates a change of the synchronisation state that did not actually occur. This grows exponentially with the threshold value THRES.
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Figure 6-2. shows the simulated LARL for all code rates, the channel error rate is set so the SNR is 1dB below the error rate required for QEF operation at the output of Viterbi decoder.
MOTOROLA 3-10
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While the SARL and RARL can be determined analytically the evaluation of the LARL is nontrivial and is best determined via simulation.
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NOTE
- 8 RARL = Synchstates x SARL - rate = 1 2
For More Information On This Product, Go to: www.freescale.com
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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For automatic rate selection the synchroniser investigates the possible synchronisation states one after the other and RARL is calculated as follows:
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Freescale Semiconductor, Inc.
Device Description
LARL (Syndrome Bits)
*
2
+
*
+ x
r=1/2, design point r=1/2, quasi error free r=1/2, worst case r=2/3, design point r=3/4, design point r=5/6, design point r=7/8, design point
1e+05

5
*
#
Freescale Semiconductor, Inc...
+
*
at m y In fo r
x x
1e+04
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2
#
5
*
2
# + * x x
1e+03
5
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THIS GRAPH NEEDS TO BE EXTENDED! THE SCALES TO SHOW THE THRESHOLD UP TO 5000 AND THE CURVES EXTRAPOLATED
0.50
1.00
1.50
2.00
2.50
THRES x 103
Figure 3-7. LARL Versus THRES At Various Design Points For rate 1/2 (worst case for the synchroniser) the results for QEF (BER = 0.0789) and 2.8 dB below (BER = 0.125) are shown extrapolated. From it can be seen that the LARL increases with decreasing SNR. For QEF operation a threshold below 5000 is sufficient to obtain less than one synchroniser error per day for a rate 1/2. 3.2.3.1.6 Lock Detection and Time-out Lock of the decoder is indicated if the state of the synchroniser has not changed for a significantly long time, this period is measured in number of syndrome bits. The time-out period can be set via the I2C register TIMEOUT, a default value of 8 is used if bit DLT in the CONFIG register is set to 0. The actual period is TIMEOUT * 211 syndrome bits.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
MOTOROLA 3-11
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Freescale Semiconductor, Inc.
Device Description
* If the accumulator value L does not reach the threshold value THRES within the period specified by TIMEOUT then it is reset and the decoder continues to indicate a locked state. * If L exceeds THRES before the end of the TIMEOUT period then an out of lock condition is declared and the synchroniser moves to the next state and restarts the synchronisation process. To avoid false lock indications, and to quickly detect out of lock situations the optimal value for TIMEOUT is SARL * 4. 3.2.3.2 Viterbi Error Correction 3.2.3.2.1 BER vs. SNR Performance Figure 3-8 shows the performance curves for each code rate as a function of Bit Error Rate (BER) versus channel Signal to Noise Ratio (SNR). The graph also shows the Quasi Error Free (QEF) operating limit at 2 * 10-4. The graph was generated assuming QPSK transmission over an AWGN channel with a normalized gain of 1 at the output of the receiver A/D. In paragraph 5.3.2.3 an example is given how to obtain a BER estimate from the QVAL values that are available from the FEC register.
Freescale Semiconductor, Inc...
MOTOROLA 3-12
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
*
+
r=1/2 r=2/3 r=3/4 r=5/6 r=7/8
BER 2 1e-01 5 2
* * + x +
x x + x * * + x

Freescale Semiconductor, Inc...
1e-02 5 2 1e-03 5 QEF 2
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x * + x + x * *
1e-04 5 2 0.00
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Eb/N0 (dB) 2.00 3.00 4.00 5.00 6.00
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Figure 3-8. BER versus SNR
3.2.3.2.2 Decoding Latency A survivor depth of 96 is used to ensure reliable error correction for highrate punctured codes such as the 7/8 code. The latency of the decoder (in symbols) is approximately 2.5 x the survivor depth (the uncertainty in the latency is due to the input FIFO which gives a range of + or - 16 symbols). NOTE This latency applies for all coding rates not just the 7/8 rate. The absolute worst case latency is thus: (2.5 x 96) + 16 = 256 symbols.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
MOTOROLA 3-13
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Freescale Semiconductor, Inc.
Device Description
3.2.3.2.3 Generator Polynomials The Viterbi decoder is designed to decode bit streams encoded using the DVB standard generator polynomials (1718, 1338) as shown in Figure 3-9.
1718
+
Data In Data Out
Freescale Semiconductor, Inc...
Table 3-3. Deletion Map For Punctured Rate 1/2 Codes
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3.2.3.2.4 Punctured Codes The Viterbi decoder is able to decode a basic rate 1/2 convolutional code and the "standard" punctured codes for a k=7 constraint length. The punctured maps are shown in the table below. Specific bits of the original rate 1/2 code sequence are periodically deleted prior to transmission according to the entries in the table, where a 0 means that the bit is deleted and a 1 means that the bit is transmitted.
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Coding Rate
1/2 2/3 3/4 5/6 7/8
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3.2.3.2.5 Rate Encoding Data Word The code rate actually being decoded by the decoder is indicated via external pins SR2..SR0 and via the I2C interface.
MOTOROLA 3-14
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1 1 11 10 110 101
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Figure 3-9. Generator Polynomials
Puncture Map
11010 10101 1111010 1000101
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
Table 3-4 shows the encoding of the rate information into a three bit word. This information is used for output information when using automatic synchronisation or for control information when the block is being externally controlled via the I2C interface. Table 3-4. Rate Encoding
Coding Rate
1/2 2/3 3/4 5/6 7/8 Automatic Data Word 000 001 010 011 100 111
Freescale Semiconductor, Inc...
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3.2.3.2.6 Input Data Format The I and Q data input to the decoder can be interpreted as either sign-magnitude or offset binary format. The choice of input format is specified by setting the IFS bit in the CONFIG register bank of the I2C interface. The default after RESET_N is to use offset binary.
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Table 3-5. I And Q Input Format
VC0[2:0]/VC1[2:0] IFS = 0 (offset binary) 000 001 010 011 100 101 110 111 IFS = 1 (sign-magnitude) 011 010 001 000 100 101 110 111 2's complement (internal format) 100 101 110 111 000 001 010 011
3.2.3.2.7 Channel SNR Measurement The synchroniser generated syndrome sequence (p0) is used to determine the channel SNR value. The average value of the number of 1's accumulated from p0 is calculated over a known period and is accessible via the I2C interface.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Interpretation
strong 0 . . weak 0 weak 1 . . strong 1
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This table is referred to throughout this document when discussing the various rates supported by the decoder.
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Notes: Automatic rate selection is only used as an input value when internal synchronisation is used. The decoder will never output 111 as a coding rate. All other states of the 3 bit data word are unused.
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MOTOROLA 3-15
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Freescale Semiconductor, Inc.
Device Description
The window length used is specified by the AVRG_PERIOD register and is interpreted as AVRG_PERIOD[3:0] * 215, the default period of 8 * 215 is used if the DAP bit in the CONFIG register bank is set to 1. The number of 1's in the syndrome stream (divided by 16) which are accumulated over the specified period may be read from the registers QVALMSB[7:0] and QVALLSB[7:0]. The estimated value of p0 is: QVAL x 2 4 p 0 = 1 - -----------------------------------PERIOD x 2 15 The value of p0 can be directly related to the signal quality for the various code rates via the curves shown in Figure 3-10. This signal quality value corresponds to the channel SNR of QPSK transmission over an AWGN channel. The curves are generated specifically for the syndrome polynomials actually used in the decoder. To derive a channel SNR value simply look up the value on the x-axis of a given p0 value for a given code rate.
Freescale Semiconductor, Inc...
MOTOROLA 3-16
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
p0 x 10-3
x + + x + * * * * * * * * *
r=1/2 r=2/3 r=3/4 r=5/6 r=7/8
+ x
900.00
x + x + x + x +
x +

850.00
800.00
Freescale Semiconductor, Inc...
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+ +x +x * +x +x** + * * ** *
750.00
650.00
600.00
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+ x * + * x + * x + * x + * * +x * x * *
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Eb/N0 0.00 2.00 4.00 6.00
Figure 3-10. p0 Versus Channel SNR 3.2.3.2.8 Accuracy of SNR Estimate The accuracy of the p0 estimate of channel SNR increases with longer averaging periods and with increased SNR. Table 3-6 shows the effect of increasing the AVRG_PERIOD for different
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
MOTOROLA 3-17
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Freescale Semiconductor, Inc.
Device Description
code rates and channel SNR. It shows the probability that the estimate from the graph is within +/- 0.1 dB of the actual channel SNR. Table 3-6. Probability Of p0 Accuracy
AVRG_PERIOD
1 2 4 8 (default) 15 # Of Samples 32768 65536 131072 262144 491520 Probability Of +/- 0.1dB Accuracy r=1/2, Eb/N0=1.2 0.541559 0.700163 0.855141 0.960214 0.995069 r=7/8, Eb/N0=3.5 0.999799 1 1 1 1
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3.2.3.3 Frame Synchronisation
3.2.3.3.2 Frame Structure and Synchronisation Scheme The MPEG-2 Transport Packet consists of one leading Sync Byte (0x47), 187 information bytes and 16 Reed-Solomon Check Bytes (for a total of 204). In addition, the Sync Byte of every eighth packet is inverted from 0x47 to 0xB8. The frame structure of the interleaved data is depicted in Figure 3-11. The synchroniser uses this structure to determine the byte and frame boundaries to synchronise the deinterleaver and the decoder and also to resolve the -ambiguity of the data within the input stream.
MOTOROLA 3-18
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3.2.3.3.1 MPEG Frame Synchroniser and Deinterleaver This section of the manual describes the Frontend of the Reed-Solomon decoder in the MC92314. The data received from the Viterbi decoder is internally a continuous stream of bits and must be segmented into blocks (MPEG-2 Transport Packets) and subsequently into bytes that the Reed-Solomon can manipulate. The Frame Synchroniser recognizes the Synchronisation Bytes (Sync Bytes) embedded in the data stream and communicates these as frame boundaries to the Reed-Solomon decoder and the other functional blocks. The 12x17 Forney Deinterleaver processes the input bit stream to break up and distribute the longer burst errors throughout the MPEG-2 packet.
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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From the table it can be seen that even using the default value for AVRG_PERIOD the probability that the p0 estimate of SNR is within 0.1 dB is 96% (even for small SNR values). For increased AVRG_PERIOD values or increased SNR values the probability is 100% for all practical purposes.
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Freescale Semiconductor, Inc.
Device Description
SYNC (1 BYTE)
DATA (187BYTES)
RS REMAINDER (16 BYTES)
SYNC (1 BYTE)
DATA (187BYTES)
RS REMAINDER (16 BYTES)
SYNC (1 BYTE)
Pseudo Random Binary Sequence Period (1504 BYTES)
Figure 3-11. MPEG-2 Frame Structure 3.2.3.3.3 Frame Synchroniser Modes The Frame Synchroniser has two operation modes: the Acquisition and Tracking Modes. The Acquisition Mode starts when an initial Sync Byte is detected and continues until a specified number of additional Sync Bytes has been found at the correct positions within a specified number of MPEG-2 transport packets. In this case the Tracking Mode is entered. The Frame Synchroniser remains in the Tracking mode as long as the (different) set of synchronisation conditions for tracking is met and maintained. Four integer parameters (set through the I2C Interface) are used to establish these two modes: Aq_Sync_Thresh, Aq_Ref_Thresh, Tr_Sync_Thresh and Tr_Ref_Thresh. Aq_Sync_Thresh and Aq_Ref_Thresh are used to set the desired level of Acquisition conditions. If Aq_Sync_Thresh Sync Byte or inverted Sync Byte matches are found in Aq_Ref_Thresh frame spaced positions (e.g. Aq_Sync_Thresh = 2 and Aq_Ref_Thresh = 8: if 2 Sync Bytes are found in 8 MPEG-2 frames or in 8 x 204 = 1632 bytes), In_Sync is signalled and the Tracking Mode is enabled. Otherwise, the correlation upon the input bit stream is continued and the Frame Synchroniser further remains out of the synchronisation state. In the Tracking Mode, Tr_Sync_Thresh Sync Byte or inverted Sync Byte matches are necessary in Tr_Ref_Thresh frame spaced positions in order to stay In_Sync. See Figure 3-12 for the state diagram of the Frame Synchroniser. The parameters Aq_Ref_Thresh (default: 8) and Tr_Ref_Thresh (default: 31) can be set between 0 and 31 and the parameters Aq_Sync_Thresh (default: 2) and Tr_Sync_Thresh (default: 3) can be set between 0 and 7.
Freescale Semiconductor, Inc...
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 3-19
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Freescale Semiconductor, Inc.
Device Description
_1_1_1
Search for 0x47 and 0xB8 in the MPEG-2 Transport Stream
Out of Sync
# of Sync Bytes found is less than Tr_Sync_Thresh occurrences in Tr_Ref_Thresh MPEG-2 frames
First Match # of Sync Bytes found is less than Aq_Sync_Thresh occurrences in Aq_Ref_Thresh MPEG-2 frames # of Sync Bytes found is equal or more than Tr_Sync_Thresh occurrences in Tr_Ref_Thresh MPEG-2 frames
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Correlate at 204 byte spaced positions
Acquisition Mode
Correlate at 204 byte spaced positions
Tracking Mode
Figure 3-12. Frame Synchroniser State Diagram 3.2.3.3.4 -Ambiguity Resolution While in the Tracking Mode, -ambiguity is also determined and resolved. As frames enter the Frame Synchroniser the number of Sync Bytes found at frame start positions are compared to the number of inverted Sync Bytes that have been identified. If three inverted Sync Bytes are found per Sync Byte occurrence, a -offset synchronisation of the Viterbi decoder or QAM Demodulator is assumed and all received bits are inverted to correct the phase mismatch at the output. 3.2.3.3.5 Frame Synchroniser Performance The False Lock Probability (going into or staying in a state of synchronisation although synchronisation is lost), Loss of Sync Probability (detecting an Out_of_Sync state in spite of being In_Sync), Acquisition Time (time needed to assert the In_Sync condition), and Loss of Sync Time (time required to detect an Out_of_Sync situation when synchronisation is lost) are primarily influenced by the parameters: Aq_Ref_Thresh, Aq_Sync_Thresh, Tr_Ref_Thresh and Tr_Sync_Thresh, and the BER out of the Viterbi decoder. Typically, in the 1632 bit (204 x 8 = 1632 bits) frame, there are an average of 12.75, including 11.75 coincidental, matches of the (inverted) Sync Byte. Assuming these matches are uniformly distributed in the frame, the number of synchronisation trials (going from the Out_of_Sync state into the Acquisition Mode, see Figure 3-12) until the correct position of the Sync Byte is found averages 12.75 times. The probability of not going In_Sync can be seen in Figure 3-13 for a BER of 5E-2 and in Figure 314 for a BER of 1 * 10-4. The value "n" represents the parameter Aq_Sync_Thresh and on the xaxis is Aq_Ref_Thresh. These figures also show the Loss of Sync Probability if the Frame
MOTOROLA 3-20
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For More Information On This Product, Go to: www.freescale.com
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# of Sync Bytes found is equal or more than Aq_Sync_Thresh occurrences in Aq_Ref_Thresh MPEG-2 frames
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
Synchroniser is in the Tracking Mode (the value "n" now corresponds to Tr_Sync_Thresh and on the x-axis is Tr_Ref_Thresh). The Acquisition Time increases with higher values of Aq_Ref_Thresh and decreases with higher MPEG-2 Transport Stream input data rates. Each of the 12.75 synchronisation trials needs the duration of Aq_Ref_Thresh (default: 8) times 204 bytes, times 8 bits/byte, and divided by the input data bit rate. At 50 Mbit/s, the time interval until the correct position of the Sync Byte is found averages 3.3 ms at a BER of 5 * 10-2.
Freescale Semiconductor, Inc...
0.1
0.001
1E-05
Probability
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1E-13
1E-15 0 10 20 Number of Frames
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Figure 3-13. Loss of Synchronisation Probability for BER=5E-2
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 3-21
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Device Description
1E-10
1E-20
1E-30
Freescale Semiconductor, Inc...
1E-40
1E-50
Probability
1E-60
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Figure 3-14. Loss of Synchronisation for BER=1E-4 The False Lock Probability is independent of the BER and is depicted in Figure 3-15 for both the Acquisition and Tracking Modes. It gives the probability that in a random data stream the specified number of sync byte values (given with the .._Sync_Thres value) in the expected distance of 204 bytes occurs in the specified window of .._Ref_Thresh packets. Note that whenever a pattern with a period of 1632 bytes is fed into the scrambler at the transmitter side, a bit pattern that accidentally matches the Sync Byte has a 1632 period as well. This applies to any 1632 byte periodical pattern.
MOTOROLA 3-22
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
EXAMPLE: Considering, for example, the case that an all zero bit stream is fed into the scrambling block at the transmitter. The Frame Synchroniser may lock falsely onto this bit pattern, if parameters Aq(Tr)_Ref_Thresh are set to eight times Aq(Tr)_Sync_Thresh or more (see "m=8n" line in Figure 3-15). .
n=1
0.1
Freescale Semiconductor, Inc...
0.001
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1E-05
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m=8n
Probability
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1E-07
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1E-09
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1E-15 10 20 Number of Frames
1E-13
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Figure 3-15. False Lock Probability
3.2.3.4 Deinterleaver 3.2.3.4.1 Deinterleaver Functionality The error protected packets of 204 bytes are interleaved in the transmitter and the Deinterleaver must process the byte stream before the Reed-Solomon decoder. The Deinterleaver is a Convolutional Forney Deinterleaver with I=12 branches. Each branch consists of a shift register with M(11-j) cells (M=17, j=branch index). Each register has a word length of eight bits so that
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
MOTOROLA 3-23
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Device Description
the data stream is deinterleaved byte wise. For synchronisation purposes, the (inverted) Sync Bytes (as well as some 16 other bytes) are always routed in the "0" branch of the Deinterleaver. Figure 3-16 depicts a conceptual diagram of the Convolutional Forney Deinterleaver.
j=0
11 X 17
8
3 X17 2 X 17 Bytes
8 bits
8 bits
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9 10 11
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p(x) = x8 + x4 + x3 + x2 +1
17
Figure 3-16. Deinterleaver Principle Block Diagram 3.2.3.4.2 Deinterleaver Latency The latency of the 12x17 Forney Deinterleaver is 17963 CLOCK cycles (not including the Frame Synchroniser synchronisation acquisition time). 3.2.3.5 Reed-Solomon Decoder
The Reed-Solomon decoder works on a shortened (204,188,8) code with Generator Polynomial g(x) = (x+0)(x+1)...(x+15), where =0x02. One Codeword consists of a total of 204 bytes, composed of 188 information bytes followed by 16 parity check bytes. Using this code, the ReedSolomon decoder is able to detect and correct up to 8 byte errors per Codeword (a byte error specifies an erroneous byte, independently of the number of corrupted bits), which can be arbitrarily distributed within the data and check locations in a Codeword. The following is a summary of the Reed-Solomon parameters: * R = 16 Check Bytes * d = 8 Detection Power * K = 188 Message Length * m = 8 Symbol Size in Bits
MOTOROLA 3-24 Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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3.2.3.5.1 Reed-Solomon Decoder Module The algorithmic parameters of the Reed-Solomon decoder used in this block were chosen according to the DVB Specifications. The arithmetic is performed using a Finite Field GF(256) of byte data which is specified by the Field Generator Polynomial:
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Freescale Semiconductor, Inc.
Device Description
* N = 204 Codeword Length * T = 8 Number of Error Corrections 3.2.3.5.2 Reed-Solomon Functional Description The architecture of the Reed-Solomon decoder is shown in Figure 3-17. The Re-Encoder consists of a Linear Feedback Shift Register (LFSR) of length 16 (bytes) with the feedback connections as specified by the Code Generator Polynomial Coefficients. For each Codeword arriving byte by byte, the Re-Encoder performs a division of this Codeword by the Code Generator Polynomial and stores the remainder. After processing the first 188 information bytes, the Encoder appends the resulting 16 remainder bytes to the byte stream. If, after processing 188 bytes, the Re-Encoder register contents are identical to the 16 last bytes of the Codeword, the Codeword is assumed to have been received without error. Otherwise, the Syndrome (the EXOR of the 16 parity check bytes) and the register contents are stored in the Syndrome RAM. From the Syndrome, the Reed-Solomon Core iteratively determines the Error Location Polynomial (ELP) and the Error Evaluation Polynomial (EEP). The roots of the ELP specify the error locations inside the Codeword. These roots are determined in the Chien Search Unit, which checks for roots by evaluating the ELP for all 255 possible field elements. Simultaneously, the EEP polynomial is evaluated. For each root found, the corresponding EEP value is used to correct the byte error at the specific bit locations. The input data is stored in the Codeword RAM (Reed-Solomon FIFO) during the operation of the Core and the Chien Search Unit in order to take account of the latencies therein. After the roots and error values are determined by the Chien Search Unit, the data is read from the FIFO, and the necessary byte corrections are performed in the Error Correction Unit. If more than 8 byte errors occur in a single frame, this is recognized by the decoder and the input data is output unchanged. In this case, the "transport_error_indicator" bit in the MPEG-2 Transport Header is set and the RERRU output shall be asserted.
Freescale Semiconductor, Inc...
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Reed-Solomon Re-Encoder LFSR Error Location and Error Evaluation Error Location and Error Correction
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Figure 3-17. Reed-Solomon Block Diagram
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 3-25
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Device Description
3.2.3.5.3 Reed-Solomon Performance Analysis The performance was evaluated by applying BPSK Modulation to the input bits and transmitting over an Additive White Gaussian Noise (AWGN) channel at different Signal-to-Noise Ratios (SNR). The results are shown in Figure 3-18. For high input byte error rates the Reed-Solomon is not able to correct errors since there are too many errors per frame. After crossing the point where the average input byte error rate becomes lower than 8/204, the error correction capability of the (204,188,8) code is used to correct most of the errors, leading to a substantial decrease in byte error rate.
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MOTOROLA 3-26
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Figure 3-18. Input Byte Error Rate versus Output Byte Error Rate
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Device Description
3.2.3.5.4 Reed-Solomon Bit Error and Bad Frame Monitor There are two parameters accessible through the I2C Interface that the Reed-Solomon decoder circuit uses to track error rates: BER_COUNT and BAD_FRAME. BAD_FRAME This parameter gives the number of bad frames that could not be decoded and corrected during an interval of frames specified through TIME_COUNT (another I2C Interface parameter register). BER_COUNT BER_COUNT is the number of bit errors within the 188 information bytes during the same interval of frames specified by TIME_COUNT. Hence, in order to determine a bit error rate, one Codeword should be counted as 188 bytes instead of 204 bytes. If more than 8 byte errors occur in a frame, BER_COUNT cannot be updated since it is not possible to determine how many bits were corrupted. To obtain a better estimate of the BER rate into the Reed-Solomon decoder block when more than 8 bytes are corrupted, BAD_FRAME and BER_COUNT should be combined. TIME_COUNT
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After reading both values immediately one after the other to ensure consistency of the results, first check the BAD_FRAME. If it contains zero there were not more than 8 wrong bytes in all the MPEG-2 packets watched in the update period completed before the read-out. The exact number of bit errors detected and corrected by the Reed-Solomon decoder is therefore given in the BER_COUNT register. To calculate the BER after the Viterbi decoder use the formula BER_COUNT / (188 * 8 (TIME_COUNT * 4 + 2)) with the number of wrong bits in the numerator and the total number of bits (188 bytes per MPEG-2 packet) in the denominator. If the BAD_FRAME is not zero there was at least one packet with more than 8 wrong bytes leading to a not correctable packet. This prevents the BER_COUNT from being updated
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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As an example, consider the calculation of the post-Viterbi BER using these registers. In the default configuration TIME_COUNT contains 255, resulting in a number of (255 * 4 + 2) = 1022 MPEG-2 packets for the update period of the BAD_FRAME and BER_COUNT registers.
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The parameter TIME_COUNT specifies the number of Codewords during which the bit errors and bad frames are counted (note that a frame is used here to denote a Codeword of 204 bytes). The number of Codewords is given by (TIME_COUNT * 4) + 2. In addition, BER_COUNT and BAD_FRAMES are updated every (TIME_COUNT * 4) + 2 Codewords only. Internally, the corresponding counters are reset and immediately work on the following (TIME_COUNT * 4) + 2 window. Both counters have overflow protection; therefore, once the maximum value is reached, it will remain stable throughout the entire period.
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MOTOROLA 3-27
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Freescale Semiconductor, Inc.
Device Description
correctly, therefore the number of wrong bits given there does not contain the wrong bits in the uncorrectable packets. Therefore the post-Viterbi BER from the above formula is not applicable. A threshold value of the post-Viterbi BER for the exact value can be obtained by taking the worst condition of 8 single bit errors leading to 8 wrong bytes in one RS packet of 204 bytes. This gives 8 / (204 * 8) ~ 4.9 * 10-3. If this threshold is kept in all packets of the update period the BER_COUNT is guaranteed to be exact and the BAD_FRAME is automatically zero. In case of more than one wrong bit in one byte the BAD_FRAME still is zero. But of more than 8 wrong bytes are detected by the RS decoder the BAD_FRAME is incremented, leading to an invalid BER calculation using the BER_COUNT. 3.2.3.5.5 Typical Selection of the Parameters for System Application For the transmission conditions specified by the DVB, there should be only one frame with more then 8 byte errors per hour of operation. Therefore, the default setting is TIME_COUNT = 255, which means that (255 x 4) + 2 = 1022 frames are checked. For a typical transmission scenario, the BER_COUNT should then include an averaged figure of the transmission quality before the Reed-Solomon, while the BAD_FRAMES value should be zero. 3.2.3.5.6 Reed-Solomon Decoder Latency The latency of the Reed-Solomon is 3557 CLOCK cycles.
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3.2.3.6.2 Descrambler/ Synchronisation Functionality The PRBS generator is applied to all data except for the MPEG-2 Transport Stream Sync Bytes and inverted Sync Bytes. The seven Sync Bytes of a superframe pass the Descrambler unchanged, although the PRBS generator operates continuously, i.e. the output of the Descrambler is temporarily disabled for the specific transmission of a Sync Byte. Therefore, the period of the PRBS generator is still kept to 1504 bytes (8 x 188). In addition to the PRBS functionality this unit also re-inverts the inverted Sync Byte occurrences, thereby removing the superframe structure. It must be pointed out that the Descrambler will take a maximum value of 7 frames to synchronise internally to the inverted Sync Byte that denotes the superframe boundaries for the correct initialization of the PRBS. This may happen even after the Reed-Solomon decoder Block has signalled a valid synchronisation state by asserting the IN_SYNC signal pin and is already providing MPEG-2 Transport Stream Bytes at the SPO[7:0] output signal pins and generating waveforms at the other related outputs. Therefore, it is recommended to wait for this period of time after Synchronisation Acquisition has been signalled by the Frame Synchroniser at the
MOTOROLA 3-28
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3.2.3.6.1 Descrambler Module To provide an even frequency spectrum distribution across the channel bandwidth and to allow for easier clock recovery, the data is scrambled prior to transmission with a Pseudo-Random Binary Sequence (PRBS) specified by the polynomial 1+x14+x15. This block performs the descrambling of the Reed-Solomon output to obtain the originally encoded data.
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Device Description
signal pins, before the decoding process of output data is initiated, e.g. within the MPEG-2 Transport Stream Demultiplexer. 3.2.3.6.3 Descrambler Latency The latency of the Descrambler is 13 CLOCK cycles.
Freescale Semiconductor, Inc...
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 3-29
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Device Description
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MOTOROLA 3-30
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
SECTION 4 DVB-T DEMODULATOR INTERFACES
Extensive control and insight into all relevant system parameters is given to the user of Motorola's single chip DVB-T demodulator by the interfaces of the IC. To control the actions of the chip several status lines as well as internal registers are provided. The information presented in this section describes the details of the external interfaces. Also all the information necessary to understand the setup of the circuit as described in Section 5 is given. According to the characteristics of the interfaces the description is separated into the (physical) control lines and software controllable registers.
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4.1 General Purpose Outputs
Motorola's M-Bus implemented in the device is functionally identical to the well-known I2C bus. It is a two wire serial and bidirectional interface for (comparatively) slow data transmission. In many STB systems it is used to exchange control information between a host processor and peripherals using only 2 package pins. The I2C bus consists of a clock (SCL) and a data (SDA) signal. Both signals are bidirectional with open-drain output. Each device can send and receive clock and data. The master of the bus generates the clock. Figure 4-1 demonstrates the bidirectional open-drain bus configuration with 2 slaves and one master. The thick lines highlight the data flow during a read transfer from Slave1 to the master.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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4.2 I2C Interface
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Even in case of non-standardised serial tuner interfaces that need only input from the system controller the whole data transmission from the system controller to the tuner can be done by using these outputs.
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Possible applications include control of the DVB-T tuner. In some applications it may be useful to prevent the tuner interface from listening to the I2C communication all the time to keep the noise introduced by the digitial signals away from the analog circuitry of the tuner. This can easily be achieved by feeding the SDA and SCL lines to the tuner via analog switches that are enabled by one of the general purpose outputs.
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Four general purpose output pins are provided that can be set via the I2C interface of the FEC block. The corresponding bits reside in the 4 MSBs of the SOFT_RESET register (address $1F in the FEC block), these bits set the outputs of the GP[3:0] pins (pin numbers 104, 102, 99 and 97) of the MC92314.
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MOTOROLA 4-1
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Rp Slave1
VDD SDA VDD SCL Master
Rp
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Slave2
The protocol consists of a sequence of high and low states and additionally of certain edge dependencies for synchronisation. If more than one master is available a certain arbitration scheme is also defined. Arbitration is not object of this document because the MC92309 works only in slave mode. Each transmission sequence is synchronised by a start condition and finished by a stop condition. The data will be transmitted byte wise. Each transmitted byte will be acknowledged by the receiving slave module.
4.2.1 I2C Functionality
4.2.1.1 Start Condition Whenever SDA goes from high to low while SCL is constant high a data transfer sequence is started. SDA SCL
MOTOROLA 4-2
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"s"
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Figure 4-1. Usual I2C Environment
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DVB-T Demodulator Interfaces
4.2.1.2 Stop Condition Whenever SDA goes from low to high while SCL is constant high a data transfer sequence is finished. SDA SCL
"p"
4.2.1.3 Transmitting "1" and "0" Whenever SDA changes its value SCL must be low.
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SDA
"0"
"1"
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start condition
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4.2.1.4 Data Transfer Sequence Each I2C bus member has a 7-Bit address. The data transfer starts with the start condition and is followed by the 7-Bit address of the slave to be selected. The 8th bit after the address determines the direction of the initiated data transfer. The selected slave has to acknowledge the successful receipt of its address. If the transfer should be a read transfer from slave to the master, the slave starts transmitting byte by byte until the master forces the stop condition. Each byte will be acknowledged by the master. A new transfer sequence can start immediately issuing a new start condition instead of the stop condition.
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SCL
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7-Bit address
data byte 1
data byte 2
1P
read access acknowledge from slave acknowledge from master acknowledge from master stop condition
: from master
: from slave
Figure 4-2. Read Sequence
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MOTOROLA 4-3
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S
start condition
7-Bit address
00
data byte 1
0
data byte 2
0P
write access acknowledge from slave acknowledge from slave acknowledge from slave stop condition : from slave
: from master
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Figure 4-3. Write Sequence
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data byte 2
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0 1S
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7-Bit address
Write Transfer data byte 1
New Read Transfer
00
data byte 1
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acknowledge from master acknowledge from master
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4.2.1.5 Accessing Registers via I2C Each internal register accessible by the I2C has an internal I2C register address. Before a register can be accessed the I2C register address must be transferred by a write sequence. After the data byte has been transmitted or received from or to the selected I2C register an additionally byte transfer can be initiated. This byte transfer will access register with the next following I2C register address. A short example describes typical I2C sequences in a short format:
MOTOROLA 4-4
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: from master
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: from slave
Figure 4-4. Combined Sequence
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read access acknowledge from slave
restart condition
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slave address is "0001101" select register "00000000" write "11110111" into register "00000000"
read "10100111" from register "00000000"
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read "00000001" from register "00000001" read "00010111" from register "00000010"
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Figure 4-5. Typical I2C Sequence
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s 00011010 l 00000000 11110111 p s 00011010 l 00000000 r 00011011 l hlhllhhh lllllllh lllhlhhh lllllllh llllllll llllllll
l l l 0 0 0 0 0 1 LEGEND s: start condition p: stop condition r: restart 0: write "0" 1: write "1" l: read "0" h: read "1" (from master perspective)
Because 2 devices out of the 3-chip set use their own I2C controllers it was decided to implement two different I2C addresses in the single chip demodulator to keep the necessary changes on the control software as small as possible. Therefore the I2C registers of the OFDM block have a different address than the registers of the FEC part. The four lower bits of the MC92314 address can be programmed by the board designer connecting the MBUSID[3..0] pins to VDD or VSS. The higher 3 bits are fixed to different patterns for the OFDM and the FEC part.
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4.2.1.6 I2C Interface of the MC92314 Despite the device works with a supply voltage of 3.3 V it can be used without any modification in an environment with a H-Level voltage of 5 V due to the 5 V tolerant I/O drivers implemented.
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4.2.1.5.1 Defining I2C Slave Address All I2C bus members must have different 7-Bit I2C addresses with the LSB defining the direction of data transfer (0: master writes into slave; 1: master reads from slave). The selection of unique addresses within the system is done by setting certain addressbits of the devices. The bits that can be set individually by the user are explained below.
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OFDM Block I2C Slave Address MBUSID3 MBUSID2 MBUSID1 MBUSID0
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MOTOROLA 4-5
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FEC Block I2C Slave Address 0 0 1 MBUSID3 MBUSID2 MBUSID1 MBUSID0
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MOTOROLA 4-6
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4.2.2 I2C Register Maps of the MC92314
As the single chip DVB-T demodulator MC92314 is the integration of Motorola's 3 chip set into one device, the register structure of its ancestors was preserved to allow as much reuse of the control software as possible. Therefore the registers are grouped into the OFDM part and the FEC part, corresponding to the MC92308 and MC92309, as described in reference [1-4].
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 4-7
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4.2.2.1 Register Map for the OFDM Part The complete register map of the OFDM block is given in Table 4-1:
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MOTOROLA 4-8
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Table 4-1. I2C Registers of the OFDM Block
Addr $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $21 $25 $26 $2F $30 $33 $34 $36 $37
Name
TPS R0 TPS R1 TPS R2 TPS R3 TPS R4 TPS R5 TPS R 6 TPS R7 TPS R 8 TPS Idx Soft Reset OFDM R0 OFDM R1 OFDM R2 CLK Coeff INT Gain Offs AFC Strt 0 AFC Strt 1 AFC Thr 0 AFC Thr 1 AGC Thr AFC Sw Sp 0 AFC Sw Sp 1 CSE R0 CSE R1 CSE R2 CSE R3 Internal AGC Fix 0 AGC Fix 1 AFC Fdbk 0 AFC Fdbk 1 AGC Fdbk 0 AGC Fdbk 1 VCXO Fix 0 VCXO Fix 1
Type
R R R R R R R R R W W R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Def
$00 $12 $1C $75 $1F $EF $00 $10 $13 $10
b7
b6
b5
b4
S[7:0] S[15:8] S[23:16] S[31:24] S[39:32] S[47:40] S[55:48] S[63:56]
b3
b2
b1
b0
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IDX[7:0]
AFCL
CLKL
TPSV
TPSL
S[67:64] SRES CONST AFC ADCM TSM CLKS ATPS UHFI
CODERATE 00 FTSE AFCS 0
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1 10 1
GUARD ASYN
PROPORTIONAL
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AGCS 1
INTEGRATOR AFC Gain Offset AFCSTART[7:0] AFCSTART[15:8]
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1 1
AGC Gain Offset
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AFCTHRESHOLD[7:0] AFCTHRESHOLD[15:8] AGCTHRESHOLD[7:0] AFCSWEEPSPEED[7:0] AFCSWEEPSPEED[15:8] CSE[7:0] CSE[15:8] CSE[23:16] CSE[31:24] 1 0 1 0 AGCFIX[7:0] 0000 AFCFEEDBACK[7:0] AFCFEEDBACK[15:8] AGCFEEDBACK[7:0] 0000 VCXOFIX[7:0] 0000 VCXOFIX[11:0] AGCFEEDBACK[11:8] AGCFIX[11:8]
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R/W R/W R/W W W W R R R R W W R/W
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4.2.2.1.1 TPS Registers 0 - 8 ($00..$08, R) According to the DVB-T specification (see reference [1-1]) the TPS data are decoded inside of the OFDM block. These data are stored in the first 68 bits of the TPS registers. The remaining
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$1F $80 $00 $C5 $D2 $DF $10S $FA $00 $00 $00 $00
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4 bits (s68 to s71) contain status information concerning the decoding process. The TPS registers are updated continuously as the TPS data are decoded from the pilot information. To achieve read access to the TPS data this update process must be suspended prior to reading. This is accomplished by a write access to the TPS index register. Following this write the desired TPS data can be read. Table 4-2. TPS signalling information and format (see reference [1-1])
Bit number
s0 s1 - s16 0011010111101110 or 1100101000010001 010111 00: Frame #1 01: Frame #2 10: Frame #3 11: Frame #4 00: QPSK 01: 16-QAM 10: 64-QAM 11: reserved
Values
Purpose/Content
Initialization bit for 2-DPSK modulation of TPS Synchronisation word for 1st and 3rd TPS block Synchronisation word for 2nd and 4th TPS block Length indicator Frame number within the superframe
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s17 - s22 s23, s24
s25, s26
s33, s34, s35 s36, s37
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s30, s31, s32
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000: 1/2 001: 2/3 010: 3/4 011: 5/6 100: 7/8 101: reserved ... 111: reserved same as above 00: 1/32 01: 1/16 10: 1/8 11: 1/4 00: 2K mode 01: 8K mode 10: reserved 11: reserved all set to `0' BCH code TPS lock TPS valid Clock/Time Sync Lock AFC Lock
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s27, s28, s29
000: Non hierarchical 001: = 1 010: = 2 011: = 4 100: reserved ... 111: reserved
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Hierarchy information (-value) Code rate, HP stream Code rate, LP stream Guard interval Transmission mode Reserved for future use Error protection TPS acquired indicator unaveraged TPS indicator Timing Synchronisation achieved lock AFC achieved lock
s38, s39 s40 - s53 s54 - s67 s68 s69 s70 s71
MOTOROLA 4-10
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Constellation
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NOTE The status bits s68 to s71 are active H, unless the hardware pins a 1 in these bits always indicates successful lock. 4.2.2.1.2 TPS Index Register ($09, W) The function of this register is twofold: Writing a value in the allowed range (0 to 8) stops automatic updates to the TPS data. The number of bytes to read is determined from the value written (x) according to 9 - x (a value of 0 corresponds to reading the complete TPS block of 9 bytes). The TPS bytes may be read in any order from arbitrary addresses but the specified number must be read. As an example consider the reading of TPS registers 0, 4 and 8:
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Write 6 to address 9 (TPS index register): Stop automatic update and prepare for 3 bytes to read.
* Read address 4 -> TPS register 4.
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4.2.2.1.4 OFDM Mode ($0B..$0D, R/W and W) These registers hold the internal settings of the OFDM block for the modulation and the guard interval. The bit assignments are shown in Table 4-3 through Table 4-5, the initial value after reset is given by the annotation (i.v.).
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CODERATE BIT[7:4] 0000: 1/2 0001: 2/3 (I.V.) 0010: 3/4 0011: 5/6 0100: 7/8 0101: RESERVED 0110: RESERVED 0111: RESERVED 1XXX: RESERVED
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4.2.2.1.3 Software Reset ($0A, W) Writing a sequence of 0 - 1 - 0 into this register issues a soft reset of the OFDM block. In this case all the internal control loops start again, but the internal values programmed into the registers are preserved.
Table 4-3. OFDM Register 0 ($0B, R/W)
GUARD BIT[3:2 CONST BIT[1:0]
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01: 1/16 10: 1/8 11: 1/4
Note that the order of reading the 3 bytes is arbitrary. After reading the 3rd byte automatic update of the TPS registers is enabled again.
00: 1/32 (I.V.)
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00: QPSK 01: 16-QAM 10: 64-QAM (I.V.) 11: RESERVED
* Read address 8 -> TPS register 8.
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* Read address 0 -> TPS register 0.
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MOTOROLA 4-11
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NOTE Note that the initial values of this register may be changed during the initialisation of the device. Note also that the ATPS Bit must be set to 0 to write into this register successfully. As the transmission parameters are available after decoding the TPS information any change in this register is beyond the normal use.
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Table 4-4. OFDM Register 1 ($0C, W)
RESERVED BIT[7:4] ASYN BIT[3] 0: MANUAL SWITCH ATPS BIT[2] 0: MANUAL LOAD AFC BIT[1] 0: COARSE ACQUISITION (I.V.) TSM BIT[0] 0: COARSE ACQUISITION (I.V.) 1: FINE ACQUISITION
Time Sync Mode [TSM]: The OFDM block has two different modes to achieve and track the time synchronisation. Depending from bit O[11] it changes automatically from coarse mode (achieve sync) to fine mode (track sync). In some rare cases it might be necessary to set the mode manually using this bit. If bit O[11] is set to 1 the Time Sync Mode bit has no effect. AFC Mode [AFC]: The OFDM block has two different modes to achieve and track the frequency synchronisation. Depending from bit O[11] it changes automatically from coarse mode (continous sweep through the available offset frequency range) to fine mode (track sync by using the pilot carriers). In some rare cases it might be necessary to set the mode manually using this bit. If bit O[11] is set to 1 the AFC Mode bit has no effect. OFDM Mode Setting [ATPS]: This bit is used to switch between Automatic mode selection (modulation and coderate set based on the decoded TPS values) and manual mode setting. If set to 0 the manual mode settings must be loaded into the corresponding bits in the OFDM Mode register 0 as shown in Table 4-3. The initial value after reset is 1, corresponding to automatic setting. OFDM Sync Mode Setting [ASYN]: The changeover from coarse to fine acquisition mode for time sync and AFC control is normally done automatically. This automatic switch can be disabled, the initial value set after reset is automatic changeover.
MOTOROLA 4-12
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0001: (I.V.)
1: AUTOMATIC 1: AUTOMATIC SETTING FROM TPS 1: FINE SWITCH (I.V.) (I.V.) ACQUISITION
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Table 4-5. OFDM Register 2 ($0D, W)
FTSE BIT[7] AFCS BIT[6] AGCS BIT[5] 0: INCR. VOLT -> INCR. GAIN 1: DECR. VOLT -> INCR. GAIN (I.V.) RESERVED BIT[4:3] UHFI BIT[2] 0: UPPER S.B. 10: (I.V.) 1: LOWER S.B. (I.V.) ADCM BIT[1] CLKS BIT[0]
0: FTS 0: INCR. FREQ. DISABLED (I.V.) 1: DECR. 1: FTS FREQ. (I.V.) ENABLED
0: INCR. VOLT -> 0: 2'S COMPLEMENT INCR. FREQ. (I.V.) 1: DECR. VOLT -> 1: OFFSET BINARY INCR. FREQ. (I.V.)
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UHF Demodulation Sideband [UHFI]: Normally the LO in the tuner's downconverter is located above the received channel. So the RF spectrum is inverted when arriving at the OFDM block. Using this register it is possible to select the appropriate sideband. The initial value is set corresponding to the inverted spectrum. AGC Slope [AGCS]: The direction of the AGC control signal to adjust the tuner's AGC amplifier can be adjusted using this register. The initial value is set that the OFDM block assumes increasing gain with decreasing voltage. AFC Slope [AFCS]: This bit sets the direction of the AFC control signal to compensate for LO drifts in the tuner. The initial value is set for the lower sideband used in the tuner. Fine Time Sync Enable [FTSE]: This bit enables the Fine Time synchronisation loop to control the VCXO via the -DAC in the device. To test the connection from the device to the tuner it is possible to disable this connection and to write into the VCXO Fix register. NOTE Please refer to Section 5 for additional details on the initialisation of the OFDM block. 4.2.2.1.5 Clock Loop Filter Coefficients ($0E, R/W) This register sets the coefficients for the clock loop filter coefficients. Bits [7:4] control the gain of the proportional part, bits [3:0] control the gain of the integrator. The coefficients actual used are of the form C + 1 * 2XXXX
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Tuner ADC Input Format [ADCM]: This register serves to adjust the input stage of the OFDM block to the ADC in the tuner. The initial value is set to 2's complement.
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OFDM Clock VCXO Slope [CLKS]: The direction of the VCXO control signal to adjust the OFDM system clock can be adjusted using this register (of course it is also possible to select the appropriate control line, see the paragraph 4.3.4 Tuner Control signals from the MC92314). Initial value is that decreasing voltage from the OFDM block is assumed to result in increasing frequency of the VCXO.
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MOTOROLA 4-13
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with `XXXX' being the programmed value (4 bit 2's compement numbers) and `C' being a constant. For a description of the filter structure see paragraph 3.2.2.3. 4.2.2.1.6 AGC/AFC Integrator Gain ($0F, R/W) This register allows control of the coefficients for the AGC and the AFC filter integrators. Bits [7:4] control the gain of the AGC integrator, bits [3:0] control the gain of the AFC integrator. The values programmed here increase or decrease the default values instead of setting the coefficients directly, therefore the default value is $00.
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4.2.2.1.11 Channel State Estimation [3:0] ($1A:$17, R/W) This registers controls the generation of soft-decision information out of the Channel State Estimation block. As the terrestrial reception is subject to several kinds of disturbance (see Section 2) the optimal setting w.r.t. e.g. to noise is not optimal w.r.t. to single tone or co-channel interference. The default values in this register are optimised for best noise performance. In Section 5 another set of values for best CCI performance is given. 4.2.2.1.12 Internal Register ($21, W) This register is used to select internal configurations of the OFDM. There's no need to use it for normal operation, but it can be used to enable the AGC Fix registers in the same way like the VCXO Fix registers described above. Refer to paragraph 4.2.2.1.13 for the value necessary. 4.2.2.1.13 AGC Fix [1:0] ($26:$25, W) This 2-byte register can be used to set the voltage at the -output for the AGC circuit in the tuner, mainly intended for test purposes, not for normal operation. To use them the value of $BA must be written to the Internal register at address $21. Afterwards the AGC Fix register can be
MOTOROLA 4-14 Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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4.2.2.1.10 AFC Sweep Speed [1:0] ($16:$15, R/W) This registers contains the increment value of the AFC offset stepsize during the sweep.
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4.2.2.1.9 AGC Threshold ($14, R/W) This register holds the compare value for the AGC module. By changing this value it is possible to alter the input peak-to-mean ratio of the OFDM time domain signal and therefore find the optimal compromise between quantisation noise and clipping.
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4.2.2.1.8 AFC Threshold [1:0] ($13:$12, R/W) This register holds the threshold value to switch off coarse AFC as a 16-bit value (register 0 at address $12 corresponds to the LS byte, register 1 at address $13 to the MS byte). By adjusting this value, it is possible to optimise the AFC acquisition time.
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4.2.2.1.7 AFC Sweep Start [1:0] ($11:$10, R/W) This registers holds the initial value of the accumulator for the coarse AFC frequency sweep algorithm. This corresponds to the start point of the sweep through the available range when the sweep starts, e.g. after a soft reset. Once synchronisation has been achieved, it may be possible to reduce the lock-in time of subsequent acquisition cycles by trying the previous lock-in value.
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used to set the analog voltage level at the AGC input of the tuner. The format is identical to the AGC Feedback register described below (12 bit width, 4 MSBs of register 1 are always 0). The following table summarises the voltage levels after the LPF in relation to the AGCS bit: Table 4-6. Voltages after the AGC LPF using the AGC Fix Register
AGC Fix Register Content -2048 (00001000 00000000) +2047 (00000111 11111111) -2048 (00001000 00000000) +2047 (00000111 11111111) AGCS 0 0 1 1 Voltage Level Lowest voltage (near 0 V) Highest Voltage (near 3 V) Highest Voltage (near 3 V) Lowest voltage (near 0 V)
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AGC Feedback Register Content -2048 (00001000 00000000) +2047 (00000111 11111111) -2048 (00001000 00000000) +2047 (00000111 11111111)
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Table 4-7. Voltages according to the AGC Feedback Registers
AGCS 0 0 1 1 Voltage Level Lowest voltage (near 0 V) Highest Voltage (near 3 V) Highest Voltage (near 3 V) Lowest voltage (near 0 V)
Note that for correct operation bit AGCS must reflect the behaviour of the tuner's AGC circuitry. Given that this setting is correct and the OFDM block is locked onto the signal the most negative value corresponds to the minimum gain of the tuner and the most positive value corresponds to the maximum gain. 4.2.2.1.16 VCXO Fix [1:0] Register ($37:$36, W) This 2-byte register can be used to set the voltage at the -output for the VCXO in the tuner, mainly intended for test purposes, not for normal operation. To use them the FTSE bit must be set to 0. Afterwards the VCXO Fix register can be used to set the analog voltage level at the VCXO input of the tuner. Again, the 4 MSBs of register 1 are always 0.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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The AGC voltage levels corresponding to the numbers depend from the value of the AGC Slope bit AGCS:
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4.2.2.1.15 AGC Feedback [1:0] Register ($34:$33, R) Similar to the AFC Feedback register these two registers represent the current position of the AGC control inside the available range (register 0 at address $33 corresponds to the LS byte, register 1 at address $34 to the MS byte). The number format is 2's complement and the number contains 12 valid bits (the 4 MSBs of register 1 are not used, they are always 0).
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4.2.2.1.14 AFC Feedback [1:0] ($30:$2F, R) These two registers represent the current offset of the internal AFC block inside the available range (register 0 at address $2F corresponds to the LS byte, register 1 at address $30 to the MS byte). Values within the available range excluding the edges represent normal operation.
at
io n
MOTOROLA 4-15
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DVB-T Demodulator Interfaces
The following table summarises the voltage levels after the LPF in relation to the CLKS bit: Table 4-8. Voltages after the VCXO LPF using the VCXO Fix Register
VCXO Fix Register Content -2048 (00001000 00000000) +2047 (00000111 11111111) -2048 (00001000 00000000) +2047 (00000111 11111111) CLKS 0 0 1 1 Voltage Level Lowest voltage (near 0 V) Highest Voltage (near 3 V) Highest Voltage (near 3 V) Lowest voltage (near 0 V)
Freescale Semiconductor, Inc...
MOTOROLA 4-16
Pr
el
im
in
ar
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In
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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fo r
m
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Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
4.2.2.2 Register Map for the FEC Part The table below describes the register map for the FEC block: Table 4-9. I2C Registers for the FEC Block
Addr 0 1 2 3 4 8 9 $A $B $C
Name
CONFIG_VIT THRESHOLD DECREMENT TIMEOUT AVG_PERIOD QVALLSB QVALMSB SYNC_VIT SELECTEDRATE FIFO_STATE
Type
R/W R/W R/W R/W R/W R R R R R/W R/W R/W R R R R/W R
Def
b7
DAP
b6
DLT
b5
DDEC
b4
DTHR
b3
IFS
b2
THRES[4:0] DEC[4:0]
b1
VSYNC[2:0]
b0
TIM[3:0] PERIOD[3:0] QVAL[7:0] QVAL[14:8] VLCK SR[2:0] VFF REF[4:0] REF[4:0] TC[7:0] BER[7:0] BAD[3:0] 0 GP2 0 GP1 0 GP0 0 RERRU FFT DEINT INSYNC RS VIT VEF
Freescale Semiconductor, Inc...
$12 TR_THRESH $13 TIME_COUNT $18 BER_COUNT $19 BAD_COUNT $1A SYNC_RS $1F SOFT_RESET
SYNC[2:0]
4.2.2.2.1 CONFIG_VIT Register ($0, W)
Pr
Read Write Access
im
in
ar
GP3
y
0
In
fo r
$11 AQ_THRESH
SYNC[2:0]
m
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7 DAP
6
5 DDEC
4 DTHRES
3 IFS
2
1
0
I2C Register Address
el
W
DLT
VSYNC[2] VSYNC[1] VSYNC[0]
$00
Default Setting After Reset:
1
1
1
1
1
1
1
1
DAP Default Average Period Select 0: Period for channel SNR measurement is defined by I2C Register AVRG_RERIOD x 215 1: Period for channel SNR measurement is 8 x 215 DLT Default Lock Time-out Select 0: Lock time-out of Node Synchroniser is defined by I2C Register TIMEOUT x 211 syndrome bits 1: Lock time-out of Node Synchroniser is 8 x 211 syndrome bits
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA 4-17
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DVB-T Demodulator Interfaces
DDEC Default Decrement Select 0: Accumulator decrement in Node Synchroniser is defined by I2C Register DECREMENT 1: Accumulator decrement in Node Synchroniser is used rate dependent from Table 3-1.. DTHRES Default Threshold Select 0: Accumulator threshold in Node Synchroniser is defined by I2C Register THRESHOLD 1: Accumulator threshold in Node Synchroniser is 8 x 29 IFS Input Format Select
Freescale Semiconductor, Inc...
0: The I-Q-Inputs G1DATA2..0 and G2DATA2..0 are interpreted as offset binary 1: The I-Q-Inputs G1DATA2..0 and G2DATA2..0 are interpreted as sign magnitude VSYNC[2:0] Decoder Rate Select 000: Select fixed Viterbi decoder rate of 1/2 001: Select fixed Viterbi decoder rate of 2/3 010: Select fixed Viterbi decoder rate of 3/4 011: Select fixed Viterbi decoder rate of 5/6
im
Read Write Access
in
4.2.2.2.2 THRESHOLD Register
7 0 6
ar
y
111: Automatic Viterbi decoder rate selection
In
100: Select fixed Viterbi decoder rate of 7/8
fo r
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5 0
4
3
2
1
0
I2C Register Address
el
Default Setting After Reset:
Pr
W
0
THRES[4] THRES[3] THRES[2] THRES[1] THRES[0]
$01
0
0
0
0
0
0
0
0
THRES[4:0] Accumulator Threshold Value When DTHRES is 0 THRES[4:0] will be used as threshold value in Node Synchroniser.
MOTOROLA 4-18
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DVB-T Demodulator Interfaces
4.2.2.2.3 DECREMENT Register
Read Write Access
7 0
6 0
5 0
4 DEC[4]
3 DEC[3]
2 DEC[2]
1 DEC[1]
0 DEC[0]
I2C Register Address
W
$02
Default Setting After Reset:
0
0
0
0
0
0
0
0
DEC[3:0] Accumulator Decrement Value
Freescale Semiconductor, Inc...
7 0
6 0
5 0
fo r
Read Write Access
m
4.2.2.2.4 TIMEOUT Register
4
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io n
When DDEC is 0 DEC[4:0] is used to decrement the accumulator in Node Synchroniser.
3
2 TIM[2]
1 TIM[1]
0 TIM[0]
I2C Register Address
0
0
ar
0
y
Default Setting After Reset:
In
W
0
TIM[3]
$03
0
0
0
0
0
4.2.2.2.5 AVRG_PERIOD Register
Read Write Access
Pr
el
When DLT is 0 TIM[3:0] is used to define the time-out for out-of-lock condition.
im
TIM[3:0] Lock Time-out Value
in
7 0
6 0
5 0
4 0
3
2
1
0
I2C Register Address
W
PERIOD[3] PERIOD[2] PERIOD[1] PERIOD[0]
$04
Default Setting After Reset:
0
0
0
0
0
0
0
0
PERIOD[3:0] SNR Measurement Period Value When DAP is 0 PERIOD[3:0] is used to define the period for SNR measurement.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
MOTOROLA 4-19
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DVB-T Demodulator Interfaces
4.2.2.2.6 QVAL Registers
Read Write Access
7 QVAL[7]
6 QVAL[6]
5 QVAL[5]
4 QVAL[4]
3 QVAL[3]
2 QVAL[2]
1 QVAL[1]
0 QVAL[0]
I2C Register Address
R
$08
Default Setting After Reset:
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc...
R
QVAL[15]
QVAL[14]
QVAL[13]
QVAL[12]
QVAL[11]
QVAL[10]
QVAL[9]
QVAL[8]
$09
0
0
0
0
0
io
n
0 0
Default Setting After Reset:
0
QVAL[15:0] SNR Measurement Result
From QVAL[15:0] it can be determined the SNR.
4.2.2.2.7 SYNC_STATE Register
im
Read Write Access
in
ar
y
In
The register is read only. A write access will not have any effect.
fo r
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at
7 0
6
5 0
4 0
3 VLCK
2 X
1 X
0 X
I2C Register Address
Default Setting After Reset:
Pr
0
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R
0
$0A
0
0
0
0
0
0
0
VLCK Node Synchroniser in Lock Indicator 0: Node Synchroniser out of lock 1: Node Synchroniser in lock Bit 2 to 0 are not documented indicators. They can have any values. The same information is provided at the output pin VLOCK. The register is read only. A write access will not have any effect.
MOTOROLA 4-20
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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4.2.2.2.8 SELECTED_RATE Register
Read Write Access
7 0
6 0
5 0
4 0
3 0
2 SR[2]
1 SR[1]
0 SR[0]
I2C Register Address
R
$0B
Default Setting After Reset:
0
0
0
0
0
0
0
0
SR[2:0] Actual Rate of Node Synchroniser
Freescale Semiconductor, Inc...
000: Viterbi decoder rate is 1/2 001: Viterbi decoder rate is 2/3 010: Viterbi decoder rate is 3/4 011: Viterbi decoder rate is 5/6 100: Viterbi decoder rate is 7/8
The register is read only. A write access will not have any effect. 4.2.2.2.9 FIFO_STATE Register
im
Read Write Access
ar
y
In
The selected rate is also visible at the output pins SR2..0
fo r
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7 0
6 0
5
4 0
3 0
2 0
1 VFF
0 VEF
I2C Register Address
in
R
0
$0C
0
Pr
Default Setting After Reset:
el
0 0 0
0
0
0
0
VFF FIFO Full Indicator 0: FIFO not full 1: FIFO overflow VEF FIFO Empty Indicator 0: FIFO not empty 1: FIFO underflow The register is read only. A write access will not have any effect.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
MOTOROLA 4-21
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4.2.2.2.10 AQ_THRESH Register
Read Write Access
7 SYNC[2]
6 SYNC[1]
5 SYNC[0]
4 REF[4]
3 REF[3]
2 REF[2]
1 REF[1]
0 REF[0]
I2C Register Address
W
$11
Default Setting After Reset:
0
1
0
0
1
0
0
0
REF[4:0] Acquisition Reference Packet Number
Freescale Semiconductor, Inc...
4.2.2.2.11 TR_THRESH Register
Read Write Access
In
fo r
m
Defines the number of MPEG-2 sync bytes which have to be found for acquisition of synchronisation.
at
io
SYNC[2:0] Number of Sync Bytes for Acquisition
n
Defines the number of MPEG-2 packets in which a sync byte is searched for acquisition of synchronisation.
7 SYNC[2]
6 SYNC[1]
5
4
3 REF[3]
2 REF[2]
1 REF[1]
0 REF[0]
y
I2C Register Address
Default Setting After Reset:
0
im
1
in
ar
W
SYNC[0]
REF[4]
$12
1
1
1
1
1
1
Defines the number of MPEG-2 packets in which a sync byte is searched to remain in sync. SYNC[2:0] Number of Sync Bytes for Tracking Defines the number of MPEG-2 sync bytes which have to be found to remain in sync.
MOTOROLA 4-22
Pr
REF[4:0] Tracking Reference Packet Number
el
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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DVB-T Demodulator Interfaces
4.2.2.2.12 TIME_COUNT Register
Read Write Access
7 TC[7]
6 TC[6]
5 TC[5]
4 TC[4]
3 TC[3]
2 TC[2]
1 TC[1]
0 TC[0]
I2C Register Address
W
$13
Default Setting After Reset:
1
1
1
1
1
1
1
1
TC[7:0] Reed-Solomon Time Count Register
Freescale Semiconductor, Inc...
7 BER[7]
6 BER[6]
In
Read Write Access
fo r
4.2.2.2.13 BER_COUNT Register
5 BER[5]
m
at
Defines the number of MPEG-2 packets during which bad frames and bit errors are counted. The number of packets is given by the formula (TIME_COUNT * 4) + 2, see paragraph 3.2.3.5.4 Reed-Solomon Bit Error and Bad Frame Monitor.
io n
4
3
2 BER[2]
1 BER[1]
0 BER[0]
I2C Register Address
Default Setting After Reset:
0
0
in
ar
0
y
R
BER[4]
BER[3]
$18
0
0
0
0
0
BER[7:0]
Reports the number of bit errors detected (and corrected) by the Reed-Solomon decoder that were found during the specified number of packets (using the TIME_COUNT register mentioned above). Only the 188 bytes of the MPEG-2 packets are considered, not the bit errors found in the checkbytes. Refer to the description of TIME_COUNT about the update intervals. The register is read only. A write access will not have any effect.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
Pr
el
Reed-Solomon Bit Error Count Register
im
MOTOROLA 4-23
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DVB-T Demodulator Interfaces
4.2.2.2.14 BAD_COUNT Register
Read Write Access
7 0
6 0
5 0
4 0
3 BAD[3]
2 BAD[2]
1 BAD[1]
0 BAD[0]
I2C Register Address
R
$19
Default Setting After Reset:
0
0
0
0
0
0
0
0
BAD[3:0]
Reed-Solomon Bad Frame Count
Freescale Semiconductor, Inc...
4.2.2.2.15 SYNC_RS Register
Read Write Access
at
io
The register is read only. A write access will not have any effect.
n
Reports the number of corrupted frames during the time interval defined by TIME_COUNT. Refer to the description of TIME_COUNT for further details.
7 0
6 0
5 0
4 0
3 0
2 RERRU
1 DEINT
0 INSYNC
fo r
I2C Register Address
m
R
$1A
Default Setting After Reset:
0
0
0
y
In
0 0
0
0
0
RERRU
The same information is provided at the output pin TRERROR. DEINT This bit indicates that the Convolutional Deinterleaver is in sync. INSYNC The same information is provided at the output pin INSYNC. The register is read only. A write access will not have any effect.
MOTOROLA 4-24
Pr
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A 1 in this bit position indicates that there were uncorrected errors in the MPEG-2 packet just output by the RS decoder.
im
in
ar
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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4.2.2.2.16 SOFT_RESET Register
Read Write Access
7 GP3
6 GP2
5 GP1
4 GP0
3 0
2 FFT
1 RS
0 VIT
I2C Register Address
R/W
$1F
Default Setting After Reset:
0
0
0
0
0
0
0
0
VIT
Freescale Semiconductor, Inc...
Writing the sequence of 0 - 1 - 0 into this bit initiates a soft-reset of the Viterbi decoder.
FFT
Like the VIT bit before this bit does a soft-reset of the FFT block.
These bits set the logic levels at the general purpose output pins.
The interface between the tuner and the DVB-T demodulator MC92314 consists of the following signals: * The overall DVB-T system clock of 256/7 ~ 36.57 MHz. * Overall DVB-T system clock divided by 2 (128/7 ~ 18.28 MHz). * 8 bit parallel ADC data (real only), positioned in the IF range using an IF of 32/7 MHz * The VCXO control signal from the OFDM block. * The AGC control signal from the OFDM block.
4.3.1 General Tuner Characteristics
To work in the appropriate way the tuner part of the DVB-T frontend has to meet the following specifications: * Noise figure: 6 dB typical. 8 dB worst case.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA 4-25
Pr
The tuner is normally programmed by a microcontroller or the overall system processor via I2C interface. It must tune to the OFDM centre frequency of the desired VHF or UHF channel, normally possible offsets are taken into account by the controller.
el
im
4.3 Tuner Interface
in
For More Information On This Product, Go to: www.freescale.com
ar
y
GP[3:0]
In
fo r
m
Like the VIT bit before this bit does a soft-reset of the RS decoder.
at
RS
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Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
* Third order input intercept point: >-10 dBm at maximum gain (i.e. when the noise figure meets the number stated above); >+10 dBm if the frontend gain is reduced by 20 dB;, >+15 dBm at 30 dB gain reduction. * Image rejection: >53 dB. * LO synthesiser step size: dependent from the offset of the OFDM center frequency w.r.t. the centre frequency of the transmission channel. * LO synthesiser phase noise: >65 dBc between 200 Hz and 2 KHz offset;
Freescale Semiconductor, Inc...
>83 dBc at 10 KHz offset; The numbers are obtained using the total LO power relative to the SSB noise power in 1 Hz bandwidth. * Frequency accuracy (measured at channel 69): +/-50 KHz maximum. All impairments of the LO's (e.g. tolerance, temperature drift and ageing) for the conversion from UHF/VHF to 1st IF and the conversion to the 2nd IF must be covered with this value.
<3.8 MHz: deviation less than +/-3 dB 4.35 MHz: rejection better than 15 dB 4.7 MHz: rejection better than 30 dB >5.3 MHz: rejection better than 70 dB
4.3.2 Clock Signals
The overall DVB-T system clock of 256/7 ~ 36.57 MHz is provided by a VCXO in the tuner and must be fed to pin 61 (CLK) of the OFDM device. It is labelled `clock' in Figure 4-6. Division by 2 provides the ADC clock signal (`clock/2') that is expected at pin 33, CLKEN18. The duty cycle for both signals must be between 40/60 and 60/40 with TTL compatible levels. As the inputs of the OFDM device are 5 V compatible either 3.3 V or 5 V signals are possible.
MOTOROLA 4-26
Pr
* Frequency response: The following frequency values are relative to the center of the OFDM signal spectrum, the frequency response values are valid for the overall tuner, i.e. from the RF input until the digital output.
el
im
* ADC output signal SNR: The `tuner-SNR' must be >33 dB. It is obtained by comparing (at the output of the ADC) the RMS of the OFDM signal (specified in the paragraph `4.3.3 Input from the Tuner Analog-to-Digital Converter') with all noise and distortion added by the tuner.
in
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* Final IF centre frequency (before ADC): 32/7 MHz for 8 MHz channel bandwidth (7.61 MHz used BW); 4 MHz for 7 MHz channels (6.66 MHz used).
y
In
* 1st IF centre frequency: For the maximum step size (as stated above), an integer multiple of the RF LO synthesiser step size.
fo r
For More Information On This Product, Go to: www.freescale.com
m
at
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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>130 dBc at offset frequencies above 1.4 MHz.
Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
clock
>=5ns
>=5ns
>=5ns
>=5ns
clock/2
Freescale Semiconductor, Inc...
ADC data
The digital output of the ADC in the tuner must meet the following characteristics: * Format: 8-bit TTL compatible, either 2's complement or offset binary. The format can be set using bit O[17] in OFDM register 2. Default setting is 2's complement. The 8 bits are fed into the ADCDATA[7:0] of the OFDM block. * Sampling frequency: 18.29 MHz = clock/2. * Clocking: See Figure 4-6. Clock frequency is clock/2. The samples are clocked into the OFDM block with the rising edge of the clock signal, using the clock/2 as enable signal. The rising edge of the 36.57 MHz clock is the active edge to clock the data into the OFDM block. Therefore the data signals should change during the falling edge of the clock/2 signal to minimise the effects of skew, as given in Figure 4-6. * Analog signal before the ADC: The centre frequency of the analog IF signal before the ADC is positioned at an IF of 4.57 MHz. The OFDM can compensate an offset in frequency, e.g. due to deviations of the local oscillator in the tuner, of +/-50 KHz. OFDM signal RMS: In the absence of noise or interference the peak to RMS ratio should be 14 dB. In an 8-bit ADC with digital level 128 (peak) this leads to a RMS digital level of 25.
4.3.4 Tuner Control signals from the MC92314
The VCXO in the tuner and the AGC amplifier are controlled by the OFDM block by differential -output lines (..P for positive and ..N for negative direction). The line giving the appropriate
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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In
4.3.3 Input from the Tuner Analog-to-Digital Converter
fo r
Figure 4-6. Clock and Data phase relationship
m
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>=5ns
MOTOROLA 4-27
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Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
polarity should be chosen and fed to a RC lowpass filter to obtain the control voltage to be fed into the tuner. Refer to Section 5 for the appropriate circuit values. Common to the VCXO and the AGC control are the following output characteristics: * Signal level: The voltage level delivered by the device is within the range [0.3 V above VSS .. 0.3 V below VDD], leading to the range between 0.3 V and 3 V for the nominal supply voltage of 3.3 V. * Maximum current provided: 4 mA 4.3.4.1 VCXO Control Loop The differential control lines for the VCXO control are pin 41 (CLKCTLP) and pin 46 (CLKCTLN). The input at the tuner must meet the following characteristics: * VCXO Pulling range: minimum +/-2 KHz, maximum +/-6 KHz. This number applies to the clock signal, not to the clock/2 signal. This range must be maintained after taking into account all possible deviations, e.g. tolerance, temperature drift and ageing. * VCXO Quiescent Frequency: to keep the lock time as short as possible the deviation of the VCXO frequency corresponding to the center value of the CLKCTL output voltage should be as close as possible to the nominal frequency of (256 / 7) MHz. For best results is is recommended not to exceed +/-10 ppm, this ensures fast response of the time synchronisation circuitry.
Freescale Semiconductor, Inc...
* AGC Range: 76 dB minimum for the worst case signal levels (this is dependent upon the sensitivity and the desired range). * Direction: The direction of pulling the OFDM block assumes can be set using Bit O[21] of OFDM register 2. Default value is decreasing voltage -> increasing gain.
4.4 MPEG-2 Output Interface of the MC92314
The interface to the MPEG-2 demultiplexer or CA processor after the DVB-T frontend consists of the following lines: * MPEG-2 Byte clock: The TRCLOCK output (pin 120) maintains the overall clock of the MPEG-2 transport stream. Its average frequency corresponds to the datarate available for the transmitted DVB-T signal.
MOTOROLA 4-28
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4.3.4.2 AGC Control Loop The differential control lines for the AGC amplifier control are pin 36 (AGCCTLP) and pin 40 (AGCCTLN). The input at the tuner must meet the following characteristics:
im
in
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* Direction: The direction of pulling the OFDM device assumes can be set using Bit O[16] of OFDM register 2. Default value is decreasing voltage -> increasing frequency.
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In
fo r
For More Information On This Product, Go to: www.freescale.com
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
* MPEG-2 Frame start: The TRSTART output (pin 125) provides one pulse at the start of each transport packet leaving the FEC block. It coincides with the syncbyte in the datastream. * Data Valid indicator: H level at the TRVALID output (pin 121) signals the presence of valid data at the output. * MPEG-2 parallel data: 8 bit parallel data exit at the TRDOUT[7:0] pins.
4.5 References
[4-1] 2K - Samples FFT Processor. Advance Information on the MC92307 FFT device, available from http://design-net.sps.mot.com/ADC/markets/DSTB/fft.html
Freescale Semiconductor, Inc...
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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in
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In
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MOTOROLA 4-29
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Freescale Semiconductor, Inc.
DVB-T Demodulator Interfaces
Freescale Semiconductor, Inc...
MOTOROLA 4-30
Pr
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In
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
For More Information On This Product, Go to: www.freescale.com
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Freescale Semiconductor, Inc.
Usage and Performance of Motorola's Single-chip DVB-T Device
SECTION 5 USAGE AND PERFORMANCE OF MOTOROLA'S SINGLECHIP DVB-T DEVICE
5.1 Remarks on the Circuit Diagram
The basic interconnections to the device are already covered in the description of the DVB-T chipset given in Section 3. In the previous sections also all the information necessary to understand the function of the complete digital frontend are given. Therefore this section deals only with additional information useful for running a practical implementation of the device.
Freescale Semiconductor, Inc...
In
20 CLKCTLP
fo r
100K
The OFDM block generates internally signals for two loops to adjust the clock VCXO and the AGC amplifier in the tuner. This is done by delivering pulse-width modulated signals with one positive and one negative branch each. Depending from the polarity required the correct branch is lowpass filtered using a simple RC filter and fed into the tuner. The voltage swing for each branch is from 0.3 V to 3 V. The circuit values were adapted during the evaluation to the ALPS tuner module, they are given in Figure 5-1:
m
at
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in
OFDM Block MC92314
ar
OFDM Clock Control Voltage 10nF 1K AGC Control Voltage 1u
im
AGCCTLP
24 300K
Pr
5.2 Initialising the Chipset
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
In this paragraph the necessary operations for the complete setup of the DVB-T device is described. During the evaluation a DVB-T tuner from ALPS was used, therefore the values are optimised for this. Other tuners may require some adaption.
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Figure 5-1. LPF values for the OFDM block
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300K
MOTOROLA 5-1
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Freescale Semiconductor, Inc.
Usage and Performance of Motorola's Single-chip DVB-T Device
5.2.1 Setup of the OFDM Block
5.2.1.1 Registers of the OFDM Block Certain registers of the OFDM block need to be programmed after a hardware reset depending from the hardware of the tuner that is used in a particular design. The registers affected together with default values for the ALPS tuner can be found in the table below: Table 5-1. Initial Setting of the OFDM Registers Register Address Register Name OFDM register 2 (O[23:16]) Clock Loop Filter Coefficients Value $D3 $FE
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$0D $0E
* TPSLOCKB (pin 141) is the most sensitive indicator, if L it shows that TPS decoding worked fine. * AFCLOCK (pin 139) & CLKLOCK (pin 138), both active H, indicate that the frequency correction unit achieved lock and the coarse time sync was successful. 5.3.1.2 Lock Status Registers * The status of the TPSLOCK pin is recorded in bit [68] of the TPS information. * Also the status of AFCLOCK & CLKLOCK are contained in bits [71] and [70] of the TPS information. Unlike the physical status pins a `1' indicates lock for all three status bits. Note that this register belongs to the TPS register bank. Simply reading the address doesn't work, refer to the description given in paragraph 4.2.2.1 Register Map for the OFDM Part for reading the TPS registers.
MOTOROLA 5-2 Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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5.3.1.1 Hardware pins
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5.3.1 Status Information of the OFDM Block
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In this paragraph the optional monitoring of the receiving conditions valid for the received transmission channel is described. It may be possible to restrict the monitoring in a stable environment to the observation of the (Transmission Error Indicator -) TEI-bit in the MPEG-2 transport stream packets, nevertheless for diagnostic purposes e.g. antenna setup the status information provided by the devices of the chipset may be helpful.
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5.3 Monitoring the DVB-T Single Chip
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After programming of these values it is recommended to do a soft-reset of the OFDM and the FFT device.
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These values are valid for an ALPS tuner with the CLKCTLP line of the MC92314 used to drive the LPF.
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NOTE
Freescale Semiconductor, Inc.
Usage and Performance of Motorola's Single-chip DVB-T Device
5.3.1.3 Usage of the AGC Feedback Register The main purpose of using the AGC Feedback information is to compare different receiving conditions (e.g. during the setup of the antenna). The differences in the AGC Feedback value are correlated with the strength of the input signal (the lower the numbers read from the AGC Feedback registers the lower the gain the tuner is set to). But this holds only in the absence of interference! If interference (echoes or strong signals in adjacent channels or a co-channel transmitter) occurs, the AGC Feedback value obviously shows a very strong signal, but the signal strength monitored has no obvious relation to the desired OFDM signal.
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5.3.2.1 Hardware Pins
* The QVAL registers provide information for an estimation of the channel quality. They have their roots in the FEC for the satellite system, therefore the internal calculations are normalised to the AWGN channel. Because the conditions for terrestrial reception are completely different the SNR values calculated with these registers don't reflect the real SNR in the terrestrial transmission, nevertheless they provide useful information about the overall channel quality. * All the functional blocks in the FEC part can be monitored: The signals VLCK, INSYNC, DEINT and RERRU are available as status bits. * The BAD COUNT register contains information on erroneous transport packets in a certain interval, its use is useful at the edges of the coverage area. 5.3.2.3 FEC Block QVAL Values corresponding to BER values In paragraph 3.2.3.2.7 a formula is given to estimate the BER from the QVAL values. Using Figure 3-10 and Figure 3-8 it is possible to estimate the BER from the QVAL values. In the table below the values for the BER of 2 * 10-4 are given for all coderates. Using these values (it is
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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5.3.2.2 Software Registers
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* TRERROR (pin 130) is the most reliable indicator for correct decoding of the MPEG-2 transport stream. H level indicates that the RS decoder detected uncorrectable errors.
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* INSYNC (pin 143): H level indicates that the Frame Synchroniser after the Viterbi decoder is in lock.
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* VLOCK (pin 142) shows the lock condition of the Node Synchroniser in the Viterbi decoder. Use it with caution, the VLOCK pin alone is not a reliable indication for error-free reception.
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5.3.2 Status Information of the FEC Block
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So to use the AGC information successfully it must be ensured that the antenna is adjusted initially towards the transmitter delivering the intended OFDM signal. Furthermore, once the OFDM is synchronised onto the transmitter and the Node synchroniser in the Viterbi decoder has locked, it is recommended to derive the quality information from the QVAL values of the Viterbi decoder.
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MOTOROLA 5-3
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Usage and Performance of Motorola's Single-chip DVB-T Device
recommended to use the moving average instead of single values) the decision below/above the QEF threshold is possible. Table 5-2. QVAL Values for BER QEF Coderate
1/ 2 2/ 3 3/ 4
p0
0.610 0.705 0.740 0.795 0.850
QVAL
$18F6 $12E1 $10A4 $0D1F $099A
Freescale Semiconductor, Inc...
5/ 6 7/ 8
If an estimate for the BER is required from the QVAL the following procedure can be used: * Calculate the p0 value from the QVAL according to the formula given in paragraph 3.2.3.2.7. * Get the corresponding Eb/N0 from Figure 3-10, take into account the different curves for the different coderates.
5.4 Performance Considerations 5.4.1 Possible Changes in the OFDM Block
5.4.1.1 Speeding up the Acquisition Time All the actions necessary to acquire the MPEG-2 transport stream out of the sampled IF signal from the tuner are performed fully automatic once the tuner is set to the appropriate channel. This includes the synchronisation of the OFDM demodulator, the VCXO and AGC loops as well as the FEC part. This fully automatic process can be adjusted to the tuner used in a certain application to result in a shorter locktime. NOTE The hints given in this paragraph lead to configuration parameters highly dependent from the tuner hardware used and from the specific application. The values found to be optimal for one application may lead to different results in another environment.
MOTOROLA 5-4
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* Using Figure 3-8 the BER estimate is available using the Eb/N0 curve corresponding to the same coderate.
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Usage and Performance of Motorola's Single-chip DVB-T Device
5.4.1.1.1 Changing AFC Sweep Start The AFC loop (described in paragraph 3.2.2.2) can be controlled by setting the parameters used during the initial sweep during acquisition. It is possible to adjust the speed as well as the starting point of the sweep (refer to paragraph 4.2.2.1.7 and paragraph 4.2.2.1.10). The current position of the AFC is reported in the AFC Feedback register (see paragraph 4.2.2.1.14). This number gives an indication of the LO offset in the tuner w.r.t. the center frequency of the current RF channel. To shorten the sweep time it is possible to use this feedback value. During normal operation or just before a channel change the value should be read by system controller and stored. As the LO offset maybe slighthly different for different RF channels, the new center frequency can be taken into account together with the feedback value to calculate an expectation for the new LO offset. Depending from the usual sweep direction this value should be decreased (upward sweep) or increased (downward sweep), e.g. by app. $120 for a deviation of 10 KHz. If the new position is close to the lower edge of the range it may be useful to chose downward sweep and to increase the number.
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Note that changing the AFC sweep start may have no effect in poor reception conditions. The reason for this is that in these cases several sweeps by the AFC circuit may be necessary. The value stored in the sweep start register is used only after a soft reset. If the sweep comes to the end of its range it starts at the opposite end instead of the sweep start position. This prevents unintentional conditions were lock can never be achieved because the position the AFC is looking for is outside of the sweep range. 5.4.1.1.2 Changing AGC Integrator Gain Additional increase in acquisition speed may be possible by changing the gain of the AGC integrator during this phase. This loop defaults to be stable in all circumstances to allow for resolving the amplitude differences of 64-QAM. The default value (2's complement number) for normal operation is a small negative number. During the acquisition phase it may be tolerable to set it to a positive value (app. $4) to increase the speed of the AGC control signal.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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These steps ensure that the AFC sweep starts near the point were the AFC circuit should find its final lock position. The deviation used must be searched by evaluating different distances, depending e.g. from the settling time of the tuner, the precision of the tuner LO or the other components that are controlled by the OFDM block like VCXO or AGC amplifier.
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* Issue a soft reset for the OFDM part to force a new AFC sweep.
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* Program the AFC start value in the appropriate register (2 byte I2C write).
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* Program the tuner to the new channel, observe possible offsets in frequency.
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* Read the AFC Feedback register and calculate the expectation for the new channel.
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This results in the following recommended procedure associated with a channel change:
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MOTOROLA 5-5
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Usage and Performance of Motorola's Single-chip DVB-T Device
Especially in reception environments impaired by echoes or CCI transmissions it is essential to decrease the value if lock has been achieved to ensure stable behaviour of the AGC loop. 5.4.1.2 Co-Channel Protection vs. Noise As already mentioned in paragraph 4.2.2.1.11 the generation of the soft-decision information for the Viterbi decoder is optimised for best noise performance. Depending from the transmission environment it may be desirable to achieve better CCI performance at a very small penalty on the noise performance. This can be achieved by changing the CSE register using the values given in the table below: Table 5-3. CSE Register Values optimised for CCI Performance
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5.4.2.2 Adjusting the MPEG Frame Synchroniser The function of this functional block is described in detail in paragraph 3.2.3.3. It works on the hexadecimal values of the MPEG-2 sync bytes ($47 and $B8 resp.) that are of course present in the normal payload. Depending on the characteristics of the MPEG-2 stream transmitted an adjustment of the AQ_THRESH or the TR_THRES registers may be necessary to prevent the MPEG frame synchroniser to lock on payload bytes erroneously. In case the frame synchroniser indicates that it is in lock and remains there the system controller may check the RERRU signal. If it persists to show values other than 0 this is either an indication that the received RF signal is so bad that no reliable reception is necessary or that (very rarely) a false lock occured.
MOTOROLA 5-6
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To shorten the time necessary for the Viterbi decoder to synchronise on the datastream simply read the coderate from OFDM register 0 and program it into the CONFIG_VIT register as it is described in paragraph 4.2.2.2.1. The time to allow the demodulator device to lock onto the TPS and to make the checked parameters readable in OFDM register 0 is dependent from the signal quality and the tuner design, it has to be investigated with the whole frontend in place.
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5.4.2.1 Fixing the Coderate for the Viterbi Decoder It is part of the usual lock procedure for the FEC to figure out the FEC parameters of the DVB-T signal received. The time necessary for this may be reduced by using the readily available FEC information transmitted via the TPS channel.
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5.4.2 Possible Changes in the FEC Block
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Register Address $17 $18 $19 $1A
Register Name CSE 0 (CSE[7:0]) CSE 1 (CSE[15:8]) CSE 2 (CSE[23:16]) CSE 3 (CSE[31:24])
Initial Value $C5 $D2 $DF $10
New Value $74 $77 $7A $01
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Usage and Performance of Motorola's Single-chip DVB-T Device
In this case reprogramming the AQ_THRES to a slightly higher forces the synchroniser in the aquisition mode again and requires a larger number of syncbytes to be found before changing to the tracking mode. Of course this reprogramming of the .._THRESH values must be repeated after a hardware reset of the MC92314.
5.5 MC92314 Performance
The overall BER performance matches the requirements as defined in the DVB-T specification (see reference [1-1]), Annex A with a degradation margin of 3 dB.
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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5.5.1.1 Typical Lock Performance The following figures show typical lock performance measured with the ALPS tuner mentioned before. Again the setup used was 64-QAM, coderate 2/3 and guard interval 1/32 in RF channel 68 (center frequency 850 MHz). In the following traces the upper channel indicates the AGC status of the tuner (AGC1, Pin#2) and the lower trace shows the RERRU pin of the FEC block.
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5.5.1 Performance in a typical Consumer Application
MOTOROLA 5-7
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Usage and Performance of Motorola's Single-chip DVB-T Device
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MOTOROLA 5-8
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Figure 5-2. Typical Lock Performance, #1 (fina2710.eps)
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Usage and Performance of Motorola's Single-chip DVB-T Device
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From the figures above it can be seen that the typical lock time from the tuner to the transport stream output is around 200 ms. 5.5.1.2 Noise and Interference Performance Using a tuner together with the single-chip device MC92314 builds a complete frontend module for terrestrial DVB reception. To obtain typical performance values for a consumer-type frontend Motorola uses DVB-T tuners from ALPS together with the MC92314 on the demonstration boards. Typical values for certain performance measurements obtained with one of this boards (tuner model TDLB7X207A) are given in the table below: Table 5-4. Typical Performance Values
PARAMETER VALUE NOTE
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Figure 5-3. Typical Lock Performance, #2 (bsta2710.eps)
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Gaussian Noise Co-Channel PAL Interference
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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19.5 dB 1 dB
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1
MOTOROLA 5-9
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Freescale Semiconductor, Inc.
Usage and Performance of Motorola's Single-chip DVB-T Device
Table 5-4. Typical Performance Values
PARAMETER VALUE NOTE
Adjacent Channel PAL Interference One Echo of 0 dB Multipath Reception
t.b.d. t.b.d. t.b.d.
NOTE
Freescale Semiconductor, Inc...
5.6 References
MOTOROLA 5-10
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2. ...
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1. Co-Channel PAL-I interference was provided via a UHF TV modulator with 75% colour bars, 1 kHz sound and PRBS Nicam. Using the the DVB-T local oscillator at the exact center frequency resulted in 1 dB (OFDM power 1 dB greater than PAL peak sync power). Changing the local oscillator frequency in small steps to simulate transmitters not synchronised resulted in a change of the protection ratio between 0 and 3 dB.
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For More Information On This Product, Go to: www.freescale.com
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The modulation scheme chosen was 64-QAM, coderate 2/3 and guard interval 1/32. The failure point was defined to be a BER of 2 * 10-4 at the output of the Viterbi decoder. The RF signal was transmitted in UHF channel 34. For the CSE registers in the MC92314 the values from Table 5-3 were used.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Electrical Characteristics
SECTION 6 ELECTRICAL CHARACTERISTICS
6.1 MC92314 Electrical Considerations
The power consumption of the device at full operation is app. 1.7 W in a typical DVB-T application, details are given below. The supply voltage for the MC92314 is 3.3 V. Using two samples of the MC92314 the current consumption in different modes of operation was measured. The supply voltage was 3.3 V. The results are given in Table 6-1 and Figure 6-1 below:
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CURRENT (mA) 460 485 510 530
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CONFIGURATION
USEFUL DATARATE (MBit/s) 8.04
SAMPLE 1 POWER (W) 1.52 1.60 1.68 1.75
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Table 6-1. Current and Power Ponsumption at different datarates
SAMPLE 2 CURRENT (mA) 470 490 520 535 POWER (W) 1.55 1.62 1.72 1.77
QPSK, coderate 2/3, G.I. 1/32 16-QAM, coderate 2/3, G.I. 1/32 64-QAM, coderate 2/3, G.I. 1/32
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64-QAM, coderate 7/8, G.I. 1/32
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16.09 24.13 31.67
It can be seen that the maximum supply current in the mode with the highest datarate doesn't exceed 535 mA, leading to a power consumption of about 1.77 W. In the figure below the mean value of both samples is drawn versus the useful datarate:
Single Chip DVB-T Demodulator - Rev. 1.3 (11/27/98)
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The figures for the useful datarate are taken from the DVB-T specifictaion reference [1-1], they give the datarate of the MPEG-2 transport stream at the output of the MC92314.
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NOTE
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MOTOROLA 6-1
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Electrical Characteristics
Current consumption of two Tristan samples over datarate, CP, 06/10/98 550
540 Current consumption in mA with 3.3 V supply voltage
530
520
Freescale Semiconductor, Inc...
510
500
480
460
450
5
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MOTOROLA 6-2
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15 20 25 Useful datarate in MBit/s according to DVB-T Specification
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470
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490
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30
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35
Figure 6-1. Current Consumption of the MC92314
Single Chip DVB-T Demodulator - Rev. 1.3 (11/27/98)
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Electrical Characteristics
6.2 MC92314 DC Electrical Specifications
t.b.d.
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/27/98)
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MOTOROLA 6-3
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Freescale Semiconductor, Inc.
Electrical Characteristics
6.3 MC92314 Timing Characteristics
The timing characteristics of the MC92314 device are given in Figure 6-2 and Table 6-2:
12
CLK
2 1
Freescale Semiconductor, Inc...
CLKEN18
3 4 3 4
ADCDATA
7
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RESB
9
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7 9 10 10 11 11
MSCL, MSDA
5
TRCLK, TRSTART, TRVALID, TRERROR TRDOUT
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MOTOROLA 6-4
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AGCCTLx, CLKCTLx
Figure 6-2. MC92314 Timing Characteristics
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/27/98)
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Freescale Semiconductor, Inc.
Electrical Characteristics
Table 6-2. MC92314 Timing
No. 1 2 3 4 5 6 5 6 7 8 9 9 10 10 10 10 11 12 Characteristic CLKEN18 to CLK setup time CLKEN18 to CLK hold time ADCDATA to CLK setup time ADCDATA to CLK hold time MSDA to CLK setup time MSDA to CLK hold time MSCL to CLK setup time RESB to CLK setup time RESB to CLK hold time CLK to AGCCTRLP/N out delay CLK to CLKCTLP/N out delay CLK to TRCLK out delay CLK to TRSTART out delay CLK to TRVALID out delay CLK to TRDOUT out delay CLK period MSCL to CLK hold time min max 6.0 -0.7 6.6 0.6 1.6 1.4 0.6 1.6 18.8 0 22.0 18.1 23.4 25.1 25.1 21.9 25.5 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Freescale Semiconductor, Inc...
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CLK to TRERROR out delay
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/27/98)
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7.8 6.9
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5.4 5.0 7.5 7.7 7.0 27.4
MOTOROLA 6-5
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Electrical Characteristics
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MOTOROLA 6-6
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/27/98)
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Freescale Semiconductor, Inc.
Mechanical Characteristics
SECTION 7 MECHANICAL CHARACTERISTICS
7.1 Outlines of the 160PQFP Package
The mechanical dimensions of the 160PQFP package (package code 864A-01) that is used for this device is shown below in Figure 7-1:
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 7-1
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Freescale Semiconductor, Inc.
Mechanical Characteristics
Y 120 121
L
81 80
P
-A,B,D-
DETAIL "A"
S
D D
S S
L
B B M H AAB
-B-
M C A-B
-A-
F
J N
S
V
0. 05(O. OO2)
0. 0. 20( 008)
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0. 0. 20( 008)
BASE METAL
D
0.13(0.005) M C A-B S D S
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DETAIL "A" 160 1 40
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SECTION B-B ROTATED 7 CCW
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41 -D-
DETAIL"B"
W U
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A
0.20(0.008) M H A-B S D S 0.05(0.002) A-B
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T -HDATUM PLANE
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B
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0.20(0.008)
M C A-B S D S
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DETAIL "C"
M
B
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DETAIL "C"
-H-
Q
-CH G
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DATUM PLANE
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0.01(0.004)
DETAIL"B"
M DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z MILLIMETERS MIN MAX 28.10 27.90 28.10 27.90 3.35 3.85 0.22 0.33 3.50 3.20 0.38 0.22 0.650 BSC 0.35 0.25 0.23 0.11 0.90 0.70 25.35 REF 5 16 0.19 0.11 0.325 BSC 7 0 0.13 0.30 31.40 31.00 0.13 ----0 31.40 31.00 --0.40 1.60 REF 1.33 REF 1.33 REF MIN INCHES MAX
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SEATING PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINSIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A-B AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
1.098 1.106 1.098 1.106 0.132 0.152 0.009 0.013 0.126 0.138 0.009 0.015 0.0256 BSC 0.010 0.012 0.004 0.009 0.028 0.035 0.998 REF 5 16 0.004 0.007 0.0130 BSC 0 7 0.005 0.012 1.220 1.236 0.005 --0 --1.220 1.236 0.016 --0.063 REF 0.052 REF 0.052 REF
MOTOROLA 7-2
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Figure 7-1. Mechanical Data of the 160QFP Package
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Mechanical Characteristics
7.2 Outlines of the 169BGA Package
The mechanical details of the BGA package are shown in Figure 7-2 and Figure 7-3 above:
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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MOTOROLA 7-3
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Mechanical Characteristics
Freescale Semiconductor, Inc...
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MOTOROLA 7-4
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Figure 7-2. 169BGA Package, Drawing #1
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Freescale Semiconductor, Inc.
Mechanical Characteristics
Freescale Semiconductor, Inc...
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Figure 7-3. 169BGA Package, Drawing #2
MOTOROLA 7-5
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Freescale Semiconductor, Inc.
Mechanical Characteristics
Freescale Semiconductor, Inc...
MOTOROLA 7-6
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Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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